Monolithic Integration of Two-Dimensional Field Effect Transistors
Restricted (Penn State Only)
- Author:
- Pendurthi, Rahul
- Graduate Program:
- Engineering Science and Mechanics
- Degree:
- Doctor of Philosophy
- Document Type:
- Dissertation
- Date of Defense:
- May 09, 2024
- Committee Members:
- Osama Awadelkarim, Major Field Member
Mark Horn, Major Field Member
Saptarshi Das, Chair & Dissertation Advisor
Joshua Robinson, Outside Unit & Field Member
Albert Segall, Program Head/Chair - Keywords:
- Monolithic Integration
M3D Integration
2D Materials
Transition Metal Dichalcogenides
TMDs
CMOS
2D CMOS
Nanofabrication
FETs
Field Effect Transistors
Devices - Abstract:
- The advancement of silicon complementary metal–oxide–semiconductor (CMOS) technology has reached nodes below 10 nm, however, further scaling poses challenges. Balancing the need for desired performance and gate electrostatics while reducing channel dimensions in three-dimensional (3D) semiconducting crystals proves challenging due to increased charge carrier scattering at the semiconductor-insulator interface. In addition, the effective manufacturing cost per transistor is rising due to the ever-increasing bill for manufacturing equipment, lithographic complexity, and high cost of process development. In this regard, two-dimensional (2D) semiconductors, such as transition metal dichalcogenides (TMDCs), are a promising alternative. The atomically thin nature and inert basal planes enable superior electrostatic control, and potentially better semiconductor-insulator interfaces, and recent demonstrations have shown industry compatible synthesis, processing, and performance of TMDC based FETs. Furthermore, the low processing temperature requirements and the capability to transfer 2D materials enable monolithic 3D integration, allowing devices to be fabricated sequentially on top of each other. In this dissertation, the potential and limitations of 2D TMDCs for FETs are explored experimentally. First, a monolithic and heterogeneous integration process is introduced, in which metal organic chemical vapor deposition (MOCVD) was implemented to grow large area n-type MoS2 and p-type vanadium doped WSe2 FETs with non-volatile and analog memory storage capabilities to achieve a non von Neumann 2D CMOS platform. Digital computing primitives such as inverter and multiplexer and neuromorphic computing primitives such as Gaussian, sigmoid, and tanh activation functions are also demonstrated, highlighting the robustness of the fabrication process. As mentioned previously, the rising cost of manufacturing and developing smaller transistors greatly limits the scalability. Herein lies the significance of three-dimensional (3D) integration—an “orthogonal scaling” approach that offers a promising strategy for elevating device integration density while effectively addressing the constraints inherent in traditional device dimension scaling. However, this integration strategy is difficult to incorporate, as the thermal processing of the devices on the top tier would cause irreparable effects on the lower tier of devices. 2D materials offer a method to circumvent this issue, as the low processing temperature preserves the performance of the underlying device. This is exemplified by several demonstrations incorporating 2D materials into a 3D architecture. First, we demonstrated a 2-tier wafer scale 3D integration based on MoS2 FETs consisting of over 10,000 devices in each tier. We also demonstrate 3-tier chips consisting of MoS2 and WSe2 FETs, and a 2-tier chip consisting of MoS2 FETs with channel length, L_CH = 45 in each tier. Along with the ability to increase the integration density, 3D integration offers vertical interconnectivity, which eases routing difficulties and decreases the length of the inter-tier vias. This enables higher bandwidth and less power loss. The dense interconnectivity offered by 3D integration is highlighted in our demonstration of dense and scaled integration through 300 nm vias with pitch < 1 µm connecting more than 300 devices in tier 1 and 2. Moreover, we have effectively implemented vertically integrated logic gates, encompassing inverters, NAND gates, and NOR gates.