The Development of Gallium Nitride Super-Heterojunction Transistors for 10-kV Blocking and 3-kV Switching
Open Access
- Author:
- Kemmerling, Jesse
- Graduate Program:
- Electrical Engineering
- Degree:
- Doctor of Philosophy
- Document Type:
- Dissertation
- Date of Defense:
- June 21, 2024
- Committee Members:
- Tom Jackson, Major Field Member
Rongming Chu, Chair & Dissertation Advisor
Suzanne Mohney, Major Field Member
Joshua Robinson, Outside Unit & Field Member
Madhavan Swaminathan, Program Head/Chair - Keywords:
- GaN
wide-bandgap
high voltage switch
MOSFET
HEMT
semiconductor switch
breakdown voltage
current collapse
on-resistance
transistor
super-heterojunction
superjunction
dynamic performance
electric field distribution
charge balance
charge balance technique
Schottky barrier diodes
dynamic on-resistance
gallium nitride
III-V semiconductor
semiconductor fabrication
TCAD
simulation
2DEG
AlGaN/GaN
high electron mobility transistors
metal-oxide-semiconductor field-effect transistors
SHJ
capacitance
field-plate
p-n junction
fast-switching
10-kV
3-kV switching
3-kV
analytical model
derivation
Ron-BV relationship - Abstract:
- Semiconductor switches are a desirable and safer solution for many industries and applications over mechanical switching. They enable fast and efficient switching of high voltage with low on-resistance operation in more compact high power density designs. Gallium nitride (GaN) is a proven capable material for high-power devices from lab to commercialization. The wide bandgap, large breakdown field, and high mobility polarization-induced two-dimensional electron gas (2DEG) at the AlGaN/GaN interface indicates GaN as a competitive solution against other semiconductors, such as silicon and silicon carbide. The GaN high electron mobility transistor (HEMT) utilizes the 2DEG for a high-speed low resistance channel. However, off-state blocking voltage is limited due to electric field crowding at the drain-side edge of the gate. The large off-state peak electric field can also induce charge trapping, effectively reducing the on-state current conduction and increasing device on-resistance once the gate is switched from the high voltage off-state to the on-state. The field-plate is a common method for reducing the peak electric field. However, it redistributes the electric field nonuniformly along the gate-to-drain voltage blocking drift region. Scaling upwards of 10 kV increases the number of plates, increasing fabrication complexity. The super-heterojunction (SHJ) for GaN is an analogue to the superjunction (SJ), historically a silicon method for increasing blocking voltage with reduced on-resistance. The SHJ is a charge-balance technique that can redistribute the peak electric field uniformly along the drift region when at an optimal charge balance condition between ionized acceptors and donors. Integration of the charge balance drift region with the 2DEG channel enables low resistance on-state conduction. This dissertation details the development of lateral GaN transistors with SHJ implementation. The development of the device design, fabrication process, and encountered problems, is described over three generations of SHJ transistors. First-generation field-effect transistors (SHJ-FET) with 100-μm-LSHJ demonstrate ~9.3 kV breakdown voltage. However, the static drain-to-source on-resistance (RDS,ON) is substantial at 194.5 Ω∙mm and current-collapse mitigation is limited to ~2 kV with 146% degradation in dynamic RDS,ON. Second-generation metal oxide semiconductor field-effect transistors (SHJ-MOSFET) maintain 10 kV blocking with a shorter 80-μm-LSHJ device and significantly improves static RDS,ON to 71.4 Ω∙mm by utilizing a double 2DEG channel design. By redesigning the gate-to-p-GaN structure to eliminate a region potentially prone to trapping, current collapse mitigation is also extended to record holding 3 kV with 123% degradation. Low figure-of-merit RDS,ONCo(tr) of ~4.9 ps indicates potential for low-loss fast switching. Third generation SHJ-MOSFETs demonstrate further reduction in RDS,ON to 57.3 Ω∙mm, enabled by (1) implementing a top-channel recessed-gate structure for bottom channel 2DEG conduction under the gate; and (2) aggressively shrinking source-to-p-GaN structure dimensions. SJ and SHJ device technologies require charging and discharging of p-type regions with holes to maintain a charge balanced drift region. The influence of hole transport on switching time is an unexplored domain in literature. In this dissertation, transient TCAD simulation of the SHJ-FET is utilized to understand the turn-on and turn-off switching behavior. The influence of (1) SHJ length, (2) hole mobility, (3) acceptor ionization energy, (4) hole capture rate, (5) charge balance condition, and (6) off-state drain voltage on turn-on and turn-off time is explored. There is little-to-no dependence on turn-off time due to abrupt pinch-off of the 2DEG channel. The turn-on time is driven by electrostatic potential in the p-type layer. A closed-form analytical model is derived to estimate the turn-on time and with dependence on the first four parameters, including the depletion region width and p-GaN thickness, is presented. The calculated and simulated turn-on time match exceedingly well. The model and simulation suggest turn-on time for 10-kV-class devices is microsecond-range.