Logic Locking of Integrated Circuits enabled by 2D Materials based Memtransistors
Open Access
- Author:
- Chakrabarti, Shakya
- Graduate Program:
- Electrical Engineering (MS)
- Degree:
- Master of Science
- Document Type:
- Master Thesis
- Date of Defense:
- October 19, 2022
- Committee Members:
- Saptarshi Das, Thesis Advisor/Co-Advisor
Abhronil Sengupta, Committee Member
Thomas La Porta, Program Head/Chair
Rongming Chu, Committee Member - Keywords:
- Integrated Circuits
Two-dimensional material
Logic Locking
Hardware Security
In-memory computing - Abstract:
- In this work, we demonstrate MoS2 based two-dimensional (2D) memtransistors as in-memory compute primitives to realize LL in 2D Integrated Circuits (ICs) comprising of programmable logic gates the likes of AND, NAND, OR, XOR, and NOT gates. The 2D memtransistors are three-terminal devices unlike the two-terminal memristor counterparts; thus, having an additional gate terminal providing both non-volatile and analog programming of conductance states along with electrostatic control of the 2D channel. Earlier demonstrations of LL based on traditional silicon complementary metal oxide semiconductor (CMOS) technology as well as emerging memristors require extensive hardware peripherals and additional input gates, creating a logical overhead making them area as well as energy inefficient. By harnessing the in-memory compute capability, demonstration of LL on the aforementioned logic gates have been performed, which can be locked/unlocked without any additional area overheads and at a miniscule energy expenditure of < 1 picojoules. With the increasing attention of chip manufacturing corporations to replace and/or augment silicon with aggressive scaling in lower technology process nodes, our demonstration of area and energy efficient LL illustrates how such secure ICs can be implemented by enabling the unique properties of the 2D memtransistors.