Non-volatile Memory Technology-based Solutions for Hardware Security and Data-intensive Accelerations
Restricted (Penn State Only)
- Author:
- Xu, Yixin
- Graduate Program:
- Computer Science and Engineering
- Degree:
- Doctor of Philosophy
- Document Type:
- Dissertation
- Date of Defense:
- May 07, 2024
- Committee Members:
- Chitaranjan Das, Program Head/Chair
Vijaykrishnan Narayanan, Chair & Dissertation Advisor
Venkatraman Gopalan, Outside Unit & Field Member
Abhronil Sengupta, Major Field Member
John Sampson, Major Field Member
Kai Ni, Special Member - Keywords:
- non-volatile memory
ferroelectric device
compute in memory
FPGA
hardware security - Abstract:
- In recent years, data-intensive applications have developed very rapidly with the emergence of a new era of AI and ML. The large amount of data in applications is driving the need for high performance, low energy consumption, and high-capacity memory and processing systems. Traditional von Neumann architectures have separate processing and memory units, which leads to high costs in terms of latency and energy. Besides, the increasing disparity between the speed of the processing and memory units (as known as the memory wall) aggravates this situation. Many novel approaches and optimizations have been proposed and shown their appealing advantages from different angles and different levels, such as 3D integration, FPGA, GPU, and CiM. Memory is the key to these revolutionary designs. With the increasingly rapid memory needs of high capacity and low energy and CMOS scaling approaching fundamental limits, emerging NVMs show their excellent advantages in enhancing data processing efficiency, preventing data loss due to power failure, and facilitating the establishment of new storage systems. Besides, data security and piracy are also critical for these data-intensive applications. Due to the nonvolatility of NVMs, the data stored in NVMs is more vulnerable than that in volatile memories as it can be retained after the power is off. Therefore, how to protect or encrypt data from malicious adversaries is an important and valuable direction to explore. To solve the aforementioned challenges, we explore and propose four works regarding high-performance computing hardware and hardware security based on FeFETs. In the first work, we focus on achieving dynamic reconfiguration in FPGA to support dynamic situations with deep learning workloads. By leveraging the intrinsic properties of FeFETs, a novel context-switching FPGA is proposed, which breaks the trade-off between chip are and reconfiguration latency existing in conventional FPGA. In the second work, we discuss the existing security issues in present NVMs. The conventional solutions to address them are mainly based on AES, which incurs significant performance and power overhead. To mitigate this, we proposed a lightweight encryption/decryption scheme by exploring in-situ memory operations with negligible overhead. The third work is an extension of the second work towards adoption in higher-density 3D memories. The encryption scheme is applied to NAND-type memory arrays and scaled to MLC for supporting higher capacity storage. Besides, the encryption scheme is integrated with CiM to support secure CiM for data-intensive computing applications. In the fourth work, we focus on the sensing mechanisms of CiM architectures and show an energy-efficient charge-domain FeFET-based MLC CiM array with multi-step sensing. By exploiting the MLC sensing, this design provides a larger sensing margin than the typical synapse sensing approach. In addition, the proposed design shows much better device variation resilience than conventional current-domain CiM and also improves inference accuracy and energy efficiency. We conduct extensive experiments and simulations to evaluate our proposed approaches. The experiment results demonstrate the feasibility of our approaches, and the simulation results show the effectiveness of our approaches and their superiority over the state of the arts in the corresponding research domains.