Physics and Technology of Strained Germanium Quantum Well FinFET for Low Power P-channel Application
Open Access
- Author:
- Agrawal, Ashish
- Graduate Program:
- Electrical Engineering
- Degree:
- Doctor of Philosophy
- Document Type:
- Dissertation
- Date of Defense:
- October 30, 2014
- Committee Members:
- Suman Datta, Dissertation Advisor/Co-Advisor
Suzanne E Mohney, Committee Member
Roman Engel Herbert, Committee Member
Jerzy Ruzyllo, Committee Member - Keywords:
- Semiconductor
Germanium
FinFET
CMOS - Abstract:
- Continual scaling of silicon (Si) complementary metal-oxide-semiconductor (CMOS) into deep sub-20nm regime meets some immense challenges which hinder the CMOS development. High performance III-V n-channel quantum well (QW) field effect transistors have been demonstrated with InGaAs channel. However, for complementary logic implementation, there is a significant challenge for identifying high mobility p-channel pMOS candidates. Among the most attractive candidates for pMOS are compressively strained InSb, InGaSb and Ge QW heterostructures which feature high hole mobility. The motivation of this work stems from establishing a comprehensive understanding of the transport in these QW heterostructures, extracting dominant transport limiting mechanisms and subsequently suggesting key design parameters that would enable the selection of the best channel material. Low field transport is experimentally analyzed and compared for compressively strained InSb and Ge QW heterostructures. Comprehensive bandstructure calculation and scattering analysis was performed incorporating the effect of strain and quantization to model the experimental mobility. Strained germanium which has very high hole mobility has been analyzed to be the promising alternative channel material for the future CMOS applications. Compressively strained Ge QW FinFETs with Si0.3Ge0.7 buffer are fabricated on 300mm bulk Si substrate with 20nm Wfin and 80nm fin pitch using sidewall image transfer (SIT) patterning process. We demonstrate (a) in-situ process flow for a tri-layer high-k dielectric HfO2/Al2O3/GeOx gate stack achieving ultrathin EOT of 0.7nm with low DIT and low gate leakage; (b) 1.3% s-Ge FinFETs with Phosphorus doped Si0.3Ge0.7 buffer on bulk Si substrate exhibiting peak uH=700 cm2/Vs, uH=220 cm2/Vs at 10^13 /cm2 hole density. The s-Ge FinFETs achieve the highest u*Cmax of 3.1x10^-4 F/Vs resulting in 5X higher ION over unstrained Ge FinFETs. Short channel performance is analyzed, discussed and benchmarked with literature.