Reliability Studies in Silicon Carbide and Silicon Power MOSFETs
Open Access
- Author:
- Ghosh, Amartya
- Graduate Program:
- Engineering Science and Mechanics
- Degree:
- Doctor of Philosophy
- Document Type:
- Dissertation
- Date of Defense:
- February 24, 2022
- Committee Members:
- Samia Suliman, Major Field Member
Jian hsu, Major Field Member
Osama Awadelkarim, Chair & Dissertation Advisor
Jifa Hao, Special Member
Albert Segall, Program Head/Chair
Rongming Chu, Outside Unit & Field Member - Keywords:
- Wide Band Gap
SiC
Reliability
Device Physics
Interface Traps
Border Traps - Abstract:
- Gate oxide reliability is a major concern in wide band gap devices such as silicon carbide (SiC) based power transistors, which limits their maximum achievable performance in several applications. These applications include power electronics converters, power systems, thermal sensors, rocket propulsion systems among many others. The first part of this thesis focusses on the assessment of SiC transistor reliability through the application of several testing protocols and characterization methods. One of the protocols employed is bias temperature instability (BTI), which is very effective in providing valuable information on the quality of the gate oxide and its interface with the SiC substrate. The parameter space for the reliability assessment includes stress voltage level and its duration, voltage signal frequency, stress temperature, and stress-to-measurement time delay. The characterization methods include current-voltage-temperature measurements and charge pumping (CP). CP was originally developed for 4-terminal transistors, however in this work we attempt to develop a modified version of CP and associated analysis software to enable its application to commercial 3-terminal transistors Threshold voltage (Vth) shifts as well as recovery observed during and after DC stress applied at different temperatures and stress levels are used to understand the dynamics of charge trapping/capture and detrapping/emission at gate oxide defects. It is deduced from the results that no new defects are created by the stress at the levels used in this study and Vth shifts are due to the injected electron capture and trapping at existing oxide border traps. Positive gate-voltage BTI induced Vth shift is observed to follow a power law on stress time with an exponent, n, dependent on stress temperature and level, such that 0.03 ≤ n ≤ 0.09. Electron emission and/or defect interactions are found to proceed with a low activation energy of the order of 5-10 meV and are suggested to be responsible for oxide charge reduction and, consequently, Vth recovery. Next, we have compared AC and DC bias temperature instability (BTI) degradations induced by stressing the channel and Junction-FET regions in 4H polytype n-channel SiC power MOSFETs. It is observed that the degradation caused by AC BTI stress is dependent on the device technology generation unlike the DC BTI stress degradation, which is found to be independent of technology generation. Also, it is found that the AC BTI stress causes more permanent damage to the device due to the creation of interface traps and border traps in contrast to DC BTI where only border traps are responsible for the degradation. The second part of this thesis is focused on identifying some common problems in silicon substrate-based power transistors, namely breakdown voltage instability and hot carrier degradations. New reliability protocols have been developed to resolve these issues. These protocols include constant current injection in the device in addition to the conventional high temperature reverse bias (HTRB) stress tests.