Development of two-dimensional transistors for neuromorphic computing and simulated annealing applications

Open Access
- Author:
- Sebastian, Amritanand
- Graduate Program:
- Engineering Science and Mechanics
- Degree:
- Doctor of Philosophy
- Document Type:
- Dissertation
- Date of Defense:
- March 25, 2022
- Committee Members:
- Mauricio Terrones, Outside Unit & Field Member
Osama Awadelkarim, Major Field Member
Patrick Lenahan, Major Field Member
Mark Horn, Major Field Member
Saptarshi Das, Chair & Dissertation Advisor
Albert Segall, Program Head/Chair - Keywords:
- 2D Materials
2D Transistors
Electrochemical Polishing
Device Variation
Probabilistic Neural Network
Bayesian Neural Network
2D Memtransistors
Simulated Annealing - Abstract:
- The recent decline in transistor scaling has motivated the exploration of novel materials, devices and computing architectures beyond the ageing Si technology based on the von-Neumann computing architecture. Scaling Si beyond 10 nm technology node has proven to be increasingly challenging owing to fundamental quantum mechanical limitations of Si. Two-dimensional (2D) layered materials such as transition metal dichalcogenides have emerged as a potential replacement for Si, owing to their atomically thin nature that enable aggressive size scaling up to the 2 nm technology. However, the nucleation of multilayer islands during the growth of 2D materials can degrade their electrostatic performance and ultimately reduce their scalability. We demonstrate a simple and self-limiting electrochemical polishing technique to thin down any arbitrary thickness of 2D materials to obtain uniform monolayers within a few seconds without compromising their atomistic integrity, and their optical and electronic properties. Additionally, to demonstrate the technological viability of 2D field-effect transistors (FETs) for integrated circuits, we evaluate the device-to-device variation across hundreds of 2D FETs and benchmark them against other demonstrations of 2D FETs and ultra-thin body Si FETs. Low device-to-device variation is observed as the result of high-quality epitaxial growth and clean transfer of 2D materials. Recent years have witnessed an increased interest in hardware accelerators, wherein instead of a general-purpose central processing unit, a task-specific hardware is used to improve implementation efficiency of various applications. These hardware accelerators greatly benefit from devices with in-memory computing capabilities and reduced power consumption. We exploit subthreshold Boltzmann transport in complementary 2D FETs to demonstrate low-power Gaussian synapses for the implementation of a probabilistic neural network. Complete tunability of amplitude, mean and standard deviation of the Gaussian synapse is achieved via threshold engineering in dual-gated 2D FETs. Additionally, memtransistors using 2D materials can enable in-memory computation. We implement a Bayesian neural network by exploiting cycle-to-cycle variation in the programming of the 2D memtransistors to realize Gaussian random number generator-based synapses. Here, 2D memtransistor-based integrated circuits are used to obtain neurons with hyperbolic tangent and sigmoid activation functions. These synapses and neurons are combined in a crossbar array architecture to realize a BNN accelerator. Metaheuristic algorithms such as simulated annealing (SA) has been implemented for optimization in combinatorial problems, especially for discreet problems. Using complementary 2D memtransistors, we develop the computing primitives necessary for energy and area-efficient hardware acceleration of SA for the Ising spin systems. We experimentally demonstrate search acceleration for ferromagnetic, antiferromagnetic, and a spin glass system using SA compared to an exhaustive search using brute force trial.