Optimizing TIQ Comparator Selection Algorithms: Balancing Transistor Size Variation To Minimize Integral Non-linearity Across Global Process Corners For A High-Speed TIQ Flash ADC
Open Access
- Author:
- Park, Jun Hyuk
- Graduate Program:
- Electrical Engineering
- Degree:
- Doctor of Philosophy
- Document Type:
- Dissertation
- Date of Defense:
- December 09, 2024
- Committee Members:
- Madhavan Swaminathan, Program Head/Chair
Tom Jackson, Co-Chair & Dissertation Advisor
Mehdi Kiani, Major Field Member
Kyusun Choi, Co-Chair & Dissertation Advisor
Daniel Cortes Correales, Outside Unit & Field Member
Wooram Lee, Major Field Member - Keywords:
- TIQ Flash ADC
TIQ voltage comparator
TIQ comparator selection algorithm
Linearity error
Non-linearity
Process Corners
Dyn2
Dyn1
CSV
SSV
RSV.
INL
DNL
RSV
IO/DS-PSVp/n
IO/DS-CSV
Dyn2/1 - Abstract:
- Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) are critical parameters for the performance of Analog-to-Digital Converters (ADCs), with low DNL and INL values ensuring high output accuracy. Furthermore, these low values contribute to reduced Total Harmonic Distortion (THD) and improved metrics such as Signal-to-Noise Ratio (SNR), Spurious-Free Dynamic Range (SFDR), Signal-to-Noise and Distortion Ratio (SNDR), and Effective Number of Bits (ENOB). However, even if the ADC is ideally designed so that all the DNL and INL values are zeros, the actual fabricated ADC chip still has linearity errors due to Process, Voltage, and Temperature (PVT) variations. These variations stem from randomness in manufacturing processes, power supply voltages, and operating temperatures during non-ideal manufacturing or real-world usage scenarios. In Threshold Inverter Quantization (TIQ) flash ADCs, the linearity errors affected by PVT variations can be better or worse by the TIQ comparator selection algorithm. This dissertation introduces new algorithms to further reduce these errors under PVT variations. The novel TIQ comparator selection algorithms proposed in this dissertation have made significant strides in enhancing the output accuracy of Flash ADCs. In a 6-bit TIQ flash ADC design, the DNL Sacrificing - Wp-Prioritized Size Variation Algorithm (DS-PSVp) successfully constrained all DNL and INL values to within ±0.25 LSB across all process corners at room temperature and standard power supply voltage, and achieved up to 49.88% improvement in worst-case INLs compared to the best existing algorithm for 6-bit design, Dyn2. Even under extreme conditions, such as ±10% power supply variations or temperatures 85◦C in the typical-typical process, the algorithm maintained this precision. For 8-bit TIQ flash ADCs, DS-PSVp and the INL Offset - Wp-Prioritized Size Variation Algorithm (IO-PSVp) achieved up to 51.36% and 24.47% improvements, respectively, in worst-case INLs under the four process corners, compared to the best existing algorithm for 8-bit design, Dyn1. All the new TIQ comparator selection algorithms prioritize balancing transistor size variation and strategize selecting switching threshold voltages (Vths) of TIQ comparators to minimize INL values of TIQ flash ADCs across the process corners. To demonstrate that high-precision flash ADC design is feasible even in technologies that allow discrete transistor sizing, all the TIQ comparator selection algorithms in this dissertation allow transistor sizing only in multiples of half-lambda. Despite this discrete sizing, the designed TIQ flash ADC with the new algorithms exhibited outstanding accuracy. This underscores the potential for TIQ flash ADCs to operate alongside digital circuits on a single substrate in such technologies. The proposed algorithms have been seamlessly integrated into specialized software packages, namely the IO/DS-CSV and IO/DS-PSVp/n TIQ comparator selection tools, specifically tailored for TIQ flash ADC designs. To support systematic follow-up research on these algorithms, this dissertation establishes a common set of terms and a standard order for TIQ comparator selection algorithms. Three authors developed five TIQ comparator selection algorithms, each with its own approach to reducing linearity error and its own terminology. Despite their similar meanings, differences in terminology have hindered further research. By standardizing the terms and order, this dissertation removes barriers for future researchers and provides a clear framework for describing the new algorithms. This dissertation is organized into seven chapters: Chapter 1 introduces the applications and objectives of TIQ ADCs; Chapter 2 provides the necessary background knowledge to help readers understand and evaluate the proposed algorithms; Chapter 3 standardizes TIQ comparator selection algorithms with the new terms and the standard order; Chapter 4 analyzes and describes the existing algorithms using the standardized terms; Chapters 5 and 6 illustrate the first proposed algorithm, INL Offset / DNL Sacrificing - Close Size Variation, and the second proposed algorithm, Prioritized Size Variation, with comparative simulation results to the other algorithms; and Chapter 7 summarizes the work completed and suggests future research directions.