A Modified Duobinary Communication System For Rapid Prototyping Using Fpgas And Asics
Open Access
- Author:
- Umar, Ashraf Ibrahim
- Graduate Program:
- Electrical Engineering
- Degree:
- Master of Science
- Document Type:
- Master Thesis
- Date of Defense:
- March 07, 2014
- Committee Members:
- Aldo W Morales, Thesis Advisor/Co-Advisor
Sedig Salem Agili, Thesis Advisor/Co-Advisor
Jeremy Joseph Blum, Thesis Advisor/Co-Advisor - Keywords:
- Duobinary
NRZ
FPGA
ASIC
Bandwidth
High-Speed
Rapid Prototyping
Transceiver
Stratix IV GT
Eye diagram - Abstract:
- High speed communication channels, including backplanes, always have distorting effects on signals being transmitted through them. This is mainly a result of the frequency dependent nature of such channels. In order to address this issue two common techniques exist: either carefully selecting the materials used in the backplane design or modifying the signal to suit characteristics of the communication channel/backplane by employing different line coding schemes and equalization. The most common line coding method is NRZ; however, as speed further increases, duobinary and PAM-4 are also promising techniques being investigated. Most of the past research in duobinary and PAM-4 was concentrated on simulations of the performance of coding and equalization techniques to compensate for the channel distortion. This proposed work focuses on rapid prototyping, using FPGAs and/or ASIC, of NRZ and duobinary coding and channel equalization. NRZ and duobinary coding are chosen because they are generally less complex than PAM-4, which makes them a good choice for higher data rates. A typical duobinary transceiver system comprises of an encoder at the transmitter and the corresponding decoder at the receiver. The complete encoderconsists of a duobinary pre-coder, which in turn includes a unit delay and an XOR gate to prevent error propagation, and a delay and add filter that converts the two level NRZ signal into a three level duobinary signal. The duobinary signal is then transmitted to the communication channel. At the receiver side, the duobinary decoder is implemented using a signal splitter, two comparators, and an XNOR gate. The duobinary signal generated is a three level signal which current commercial FPGAs are not capable of handling. In order to solve this problem, a simple new architecture of a duobinary system to be used with the commercial, off-the-shelf FPGAs is proposed. The standard duobinary system architecture is modified by placing the duobinary encoder after the transmit equalization, before the channel, while the duobinary decoder is placed immediately after the channel, before receiver equalization is performed. This scheme offers the advantage of allowing us to use the FPGA equalizers in the NRZ coding without having to modify them to support the three-level duobinary signal. Hence, this modified architecture takes advantage of the well-developed digital signal processing blocks in commercial FPGAs while allowing faster development times. The duobinary encoder and decoder can be built in an ASIC and interfaced with the FPGA. Simulation of this architecture is performed in Simulink, and results obtained show that hardware implementation of such architecture is feasible as the transmitted data is reliably recovered at the receiver. To accomplish this research, two software tools were used, MATLAB Simulink and Altera’s Quartus. The FPGA board used was a Stratix IV GT SI Development board with the EP4SG210040I1 chip. Simulink was used for the NRZ simulation and Quartus for hardware implementation. Two real-world channels were used: a 29 in Megtron-6 Caltrace board and a 32 inch backplane both provided by FCI electronics. Eye diagram scopes in Simulink are used to view the simulation results. The transceivers of the Stratix IV GT SI board were run at 5.65 Gbps and 11.3 Gbps using both channels to verify proper operation and also to demonstrate the equalization features within the transceivers. NRZ measurements were taken with the DSA 8200 Tektronix Time Domain Reflectometer. A correlation between the simulated and measured NRZ data is made and the results show a high degree of correlation. The BER for NRZ and duobinary were also computed for both channels the results were comparable; however, the duobinary uses half of the bandwidth.