Experimentally Calibrated Simulation Of Zno Thin Film Transistors Including Traps

Open Access
Author:
Liu, Yi-chun
Graduate Program:
Electrical Engineering
Degree:
Doctor of Philosophy
Document Type:
Dissertation
Date of Defense:
December 12, 2013
Committee Members:
  • Thomas Nelson Jackson, Dissertation Advisor
  • Kultegin Aydin, Committee Member
  • Joan Marie Redwing, Committee Member
  • Jerzy Ruzyllo, Committee Member
  • Clive A Randall, Committee Member
Keywords:
  • Thin film transistor simulation
  • oxide TFT simulation
  • oxide thin film transistor
  • oxide TFTs
  • oxide semiconductor traps.
Abstract:
Oxide based semiconductor thin film transistors are of interest because of their high mobility, and compatibility with flexible substrates. The role of contact barriers and carrier traps on these devices are unclear. In this work we have self-consistently connected simulations of the effect of contact barrier and traps to experimental results. For this work, we fabricated zinc oxide thin film transistors (TFTs) on glass substrates. We used Al2O3 and ZnO deposited by weak reactant plasma enhanced atomic layer deposition (PEALD) at 200◦C with process details reported earlier [25]. After device fabrication we measured the device drain current versus gate bias and drain current versus drain bias for several values of gate bias, from room temperature to 200 C. We also measured gated transmission line characteristics and quasi-static capacitance voltage (QSCV) characteristics for large geometry TFTs. The QSCV characteristics show a large capacitance overshoot near the channel accumulation voltage. Capacitance overshoot is expected in TFTs due to the transmission line structure of the channel resistance – gate capacitance combination [26]. However, the overshoot is observed in these devices even for sweep speeds as low as 10-2 V/S, much slower (several orders of magnitudes) than would be expected for a device with no contact barrier. Two-dimensional device simulation using Synopsis TCAD Sentaurus Device also predicts a capacitance overshoot only for a much faster gate voltage sweep (> 102 V/S). This suggests the presence of a contact barrier or trap. Transmission line characteristics are also strongly influenced by contact barriers. However, simulations of gated transmission lines even with large contact barriers do not reproduce the experimentally observed slow turn-on of the total channel resistance. To reproduce this characteristic we found we must add a significant deep level trap and some tailing near the conduction band edge. This distribution explains the exponential dependence of the transfer length method (TLM), the variable temperature IDVG measurements, the thickness dependence, and the transient current overshoot. The self heating of TFT on glass substrates is a well known effect. The threshold voltage of our device is already changing with temperature, and it is likely to be enhanced due to self-heating. Hence, pulse measurements were performed to remove contamination of self-heating. The data can be fit with four different small traps. With the experience of characterization of PEALD ZnO TFTs, a systematic characterization approach was used to find the trap density of state of devices with several different processes. Those includes: tri-layer processed PEALD ZnO TFTs and Air Force Research Laboratory (AFRL) pulsed laser deposited (PLD) zinc oxide TFTs. The trap DOS of tri-layer processed devices is similar to PEALD baseline devices. The temperature dependent measurements of AFRL high mobility devices, which has a completely different trap distribution, was fit by a single Gaussian distribution, and optical absorption coefficient was used to verify the distribution.