Fabrication, Characterization And Physics Of III-V Tunneling Field Effect Transistors For Low Power Logic And RF Applications

Open Access
Rajamohanan, Bijesh
Graduate Program:
Electrical Engineering
Doctor of Philosophy
Document Type:
Date of Defense:
March 07, 2014
Committee Members:
  • Suman Datta, Dissertation Advisor
  • Roman Engel Herbert, Committee Member
  • Theresa Stellwag Mayer, Committee Member
  • Noel Christopher Giebink, Committee Member
  • voltage scaling
  • low power
  • high performance
  • transistor
  • steep slope
  • tunnel FET
Fundamental physics sets the limit on the minimum sub-threshold swing of MOS transistor to 60mV/decade at room temperature. As a result, supply voltage scaling to reduce the power dissipation in the chip comes at the penalty of increased static power dissipation. At the same time, consumer demand for higher performance and lower power microchips is driving the need to continue scaling CMOS technology. Two possible approaches to solve the supply voltage scaling issue are: (1) Transport enhancement through high mobility material systems. (2) Threshold voltage scaling through steep switching devices. Tunneling field effect transistors (TFET) based on inter band tunneling of carriers are a promising candidate to realize steep switching slope and thus enable supply voltage scaling. In particular, tunneling transistors within the III-V compound semiconductor system are of interest since the tunneling efficiency is high due to the direct bandgap and lower effective mass of tunneling carriers. Further, wide range of compositionally tunable tunneling barrier height is possible within the III-V material system. This dissertation focusses on experimental investigation of III-V n-channel and p-channel TFET targeting low power logic as well as RF applications. Gate stack engineering for demonstration of steep switching slope in In0.65Ga0.35As/GaAs0.4Sb0.6 n-channel TFET is discussed. In0.9Ga0.1As/GaAs0.18Sb0.82 near-broken-gap n-channel TFET with enhanced ON state performance is then presented. Further, a novel planarization scheme to incorporate co-planar waveguide structure in vertical TFET is also introduced and high frequency switching in In0.9Ga0.1As/GaAs0.18Sb0.82 n-channel TFET demonstrated. Impact of tunnel barrier engineering on the low frequency noise performance of n-channel TFET is then investigated through experiments and analytical modeling. Strategy to improve high-κ/GaAsxSb1-x interface for p-channel TFET demonstration is then presented. Electrical and material characterization of p-channel GaSb, In0.65Ga0.35As/GaAs0.4Sb0.6 and InAs/GaSb TFETs incorporating the proposed gate stack is discussed. A physics based analytical model is also introduced to gain insight into the output characteristics of III-V TFET.