Tackling the Challenges in Enabling Processing in Memory in DDR-DRAM Systems
Restricted (Penn State Only)
- Author:
- Balakrishna Rai, Siddhartha
- Graduate Program:
- Computer Science and Engineering
- Degree:
- Doctor of Philosophy
- Document Type:
- Dissertation
- Date of Defense:
- October 04, 2024
- Committee Members:
- Chitaranjan Das, Program Head/Chair
Vijaykrishnan Narayanan, Major Field Member
Mahmut Kandemir, Major Field Member
Anand Sivasubramaniam, Chair & Dissertation Advisor
Saptarshi Das, Outside Unit & Field Member - Keywords:
- Processing in Memory
Bank level In Memory Processing
DRAM
Memory
NUMA capability for Bank Level In Memory Processing
LLM - Abstract:
- With the memory wall becoming more daunting with the growing imbalance between processor and memory speeds, researchers are exploring innovative architectures to combat this problem. One such architectural paradigm is Processing-in-Memory(PIM) wherein the compute is moved as close to the data as possible be it caches, DRAM, SSD etc. In this direction, this dissertation aims at tackling the challenges that are present in incorporating PIM within DDR-DRAM hierarchy. Recognizing that there are multiple options with regard to PIM in DRAM the first work carries out a design space exploration for integrating general purpose cores within the DRAM hierarchy and identifies an architecture - BLIMP - that will be the focus for future exploration. The second work identifies the lacunae in this architecture - lack of inter bank communication - and proposes to provide NUMA capability to all the banks within DIMM and enable execution of applications previously not amenable to a BLIMP-style execution. The third work examines the feasibility of BLIMP-style architectures for accelerating inference in LLMs and addresses the challenges involved. The third work is a stepping stone for future research that will extend these architectures to disaggregated memory systems.