Engineering Hole Injection and Transport in Low-dimensional Material Transistors
Open Access
- Author:
- Oberoi, Aaryan
- Graduate Program:
- Engineering Science and Mechanics
- Degree:
- Doctor of Philosophy
- Document Type:
- Dissertation
- Date of Defense:
- May 01, 2024
- Committee Members:
- Albert Segall, Program Head/Chair
Osama Awadelkarim, Major Field Member
Patrick Lenahan, Major Field Member
Morteza Kayyalha, Outside Unit & Field Member
Saptarshi Das, Chair & Dissertation Advisor - Keywords:
- p-Type 2D FET
Contact Engineering
Interface Engineering
Charge Transfer Doping
p-Type Doping
Low-dimensional Materials
2D materials
Strain
Scaling
Channel Length Scaling
Tungsten Diselenide
Molybdenum Diselenide
WSe2 p-Type FETs
Work-function Engineering
p-Type 2D Transistors
Capacitance-Voltage Measurements
Carbon Nanotubes
Interface Trap Density
Interface Traps
Conductance Frequency Measurements
Defect Density Analysis
CNT FETs
Annealing
Trap Density Reduction
Oxide Capping
Hole Injection
Hole Transport - Abstract:
- In response to the slowdown in transistor footprint scaling, and the increasing computational demands, advanced device development for high-performance and low-power logic applications has routed towards stacking of complementary Silicon (Si) nanosheets. However, traditional Si technology is reaching a tipping point owing to its thickness scaling limitations. Alternative device geometries proposed to reduce leakage while improving electrostatics require materials with beyond-Si capabilities. The utilization of novel, inherently-low-dimensional, semiconducting channel materials with superior electronic properties such as 2D Transition Metal Dichalcogenides (TMDs) and 1D Carbon Nanotubes (CNTs) have been proposed to extend the technology roadmap beyond Si. Conversely, innovative approaches to integrate memory and logic functionalities are worth exploring to address computation demands by tackling data-transfer bottlenecks. Furthermore, always-ON, edge devices, connected across platforms in this digital age, pose a serious security threat. Hence, a ground-up makeover in the next-generation of electronics powered by beyond-Si TMD materials is implemented through a single logic transistor capable of integrating memory, sensing, and security primitives. However, for beyond-Si-CMOS technology the need for enhancing p-type (hole) transport in 2D field-effect transistors (FETs) is identified as a critical yet challenging aspect. Tungsten Diselenide and Molybdenum Diselenide are proposed as promising 2D channel materials due to the more favorable Fermi-level pinning behavior near valence band edge. Techniques such as work-function engineering with the use of Palladium and contact interface optimization with the incorporation of Selenium, are explored to statistically improve hole injection efficiency. Following this strategy, a 3X reduction in contact resistance is achieved, down to 16 kΩ µm. Further, the research delves into threshold voltage engineering of p-type 2D channels using electrostatic modulation, gate dielectric optimization, and charge transfer oxide capping to achieve precise control over threshold voltage. Oxides of Molybdenum, Tungsten, and Germanium are studied in detail for their charge transfer mechanisms into the TMD channel. A large range in threshold voltage is achieved to modulate device behavior between high-performance and low-power operation with current switching ratio over 8 orders in magnitude. Precise layer engineering strategies are also elaborated, aiming to refine the transport properties of p-type transistors through uniform bilayer growth and layer functionalization techniques. Monolayer oxidation by plasma treatment of bilayer WSe2 channel with Palladium contacts, reduces contact resistance by 9X whereas functionalization by annealing in NO environment reduces contact resistance down to 3.5 kΩ µm while maintaining current switching ratio over 6 orders in magnitude. Following this, an approach to achieving high-performance p-type 2D FETs is completed. Finally, interface characterization in 1D CNT channels is discussed, presenting methods to mitigate interface defects by post-process annealing. Furthermore, temperature-dependent impedance analysis is employed to assess defect densities across the semiconductor energy gap. This concludes by underscoring the importance of interface characterization in all-interface devices such as devices on low-dimensional channel materials. This work aims to highlight the potential of low-dimensional materials for beyond-Si-CMOS logic.