Optimizing Quantum Circuit Execution: Advanced Compilation Strategies and Hardware Matching
Restricted (Penn State Only)
- Author:
- Khadirsharbiyani, Soheil
- Graduate Program:
- Computer Science and Engineering
- Degree:
- Doctor of Philosophy
- Document Type:
- Dissertation
- Date of Defense:
- September 17, 2024
- Committee Members:
- Antonio Blanca, Professor in Charge/Director of Graduate Studies
Sarah Shandera, Outside Unit & Field Member
Chitaranjan Das, Major Field Member
Mahmut Kandemir, Chair & Dissertation Advisor
John Sampson, Major Field Member
Chunhao Wang, Major Field Member - Keywords:
- Quantum Computing
Quantum circuit compilation
Iterative compilation framework
Quantum circuit reliability
Quantum error mitigation
Machine learning for hardware matching - Abstract:
- This dissertation contributes significantly to the field of quantum computing by enhancing the methodologies used to compile quantum circuits. Traditional methods typically involve a single compilation pass, but this research introduces an innovative iterative compilation framework. This approach significantly improves the reliability of quantum circuits by refining their performance through successive compilation cycles, without introducing the additional errors commonly associated with earlier techniques. Each cycle in this framework leverages accumulated insights to incrementally enhance the circuit's functionality. Central to this thesis is the development of a novel strategy for managing crosstalk, interference from overlapping quantum operations, which can notably impair the functionality of quantum circuits. Traditional compilation processes often fail to account for dynamic interactions within the circuit. However, the iterative compilation method introduced in this research utilizes data from initial compilations to better identify and mitigate crosstalk more effectively. This method directly addresses the issue of crosstalk without incurring the costs associated with traditional, less nuanced approaches. Moreover, this dissertation presents a groundbreaking technique for the strategic placement of dynamic decoupling gates. These gates are critical in stabilizing qubits and minimizing errors during idle periods. Unlike previous methods that required executing multiple circuit variations to identify optimal gate placements, the new approach performs a thorough analysis of crosstalk to efficiently pinpoint the most effective positions for these gates. This innovation significantly reduces the time and computational resources required for optimizing circuit configurations. The research further develops a multi-output ranking model that leverages machine learning to pair quantum circuits with the most appropriate hardware. Quantum processors vary widely in their capabilities, influenced by distinct error profiles and operational characteristics. The model proposed evaluates these variables to recommend the most suitable processor for each circuit, thereby boosting the reliability and efficiency of quantum computations. In summary, this dissertation establishes a refined quantum compilation framework that markedly improves the reliability of quantum circuit outputs. By introducing innovative compilation techniques and utilizing advanced strategies for dynamic decoupling and hardware matching, this work lays the groundwork for more reliable and efficient quantum computing, specifically tailored to the strengths of individual processors. This comprehensive approach not only tackles immediate challenges in quantum computing but also contributes to the broader objective of achieving practical quantum supremacy, paving the way for future advancements in the field.