Emerging Ferroelectric Device and Circuit Solutions for Data-intensive Applications
Restricted (Penn State Only)
- Author:
- Xiao, Yi
- Graduate Program:
- Computer Science and Engineering
- Degree:
- Doctor of Philosophy
- Document Type:
- Dissertation
- Date of Defense:
- May 03, 2024
- Committee Members:
- Chitaranjan Das, Program Head/Chair
Kai Ni, Special Member
Vijaykrishnan Narayanan, Chair & Dissertation Advisor
Susan Trolier-McKinstry, Outside Unit & Field Member
Tom Jackson, Outside Field Member
Abhronil Sengupta, Major Field Member - Keywords:
- ferroelectric memory
FeRAM
FeFET
FTJ
emerging non-volatile memory - Abstract:
- In recent years, data-intensive applications related to artificial intelligence (AI) have been widely adopted in daily life. However, facing the post-Moore era of electronics, the conventional Von Neumann architecture cannot meet the demand for such data-intensive applications due to its bottlenecks. The large latency and high energy consumption caused by frequent data transfer between storage and computation units limit the system’s performance. Therefore, an innovative non-Von Neumann computing architecture based on emerging NVM technologies has been proposed as a promising solution for these limitations. Compared to other emerging non-volatile memory (NVM) technologies, ferroelectric-based memories, especially doped HfO2 based, have demonstrated excellent properties in low write energy and high complementary metal–oxide–semiconductor (CMOS) compatibility, which makes them competitive candidates for efficient non-Von Neumann computing. Besides, the multi-domain property of the ferroelectric material offers opportunities as the analog synaptic weight cell which is the key component in neuromorphic computing. There are three main kinds of developed ferroelectric memories: ferroelectric tunnel junction (FTJ), ferroelectric field-effect transistor (FeFET), and ferroelectric random-access memory (FeRAM). In my works, device models are built to capture their corresponding mechanisms and then circuit simulations are implemented based on them. My works are supposed to pave the way for ferroelectric-based non-Von Neumann computing solutions of data-intensive applications. Most FTJ models lack predictive capability due to their incomplete capture of the dynamic polarization switching in a multi-domain ferroelectric thin film and the multi-band tunneling transport, limiting their usage in write-aware design optimizations. In my first work, I demonstrate: i) a predictive metal-ferroelectric-interlayer-semiconductor (MFIS) FTJ model by incorporating a polarization-switching module and a multi-band tunneling module which is calibrated with device data on both n-type and p-type substrates; ii) asymmetric polarization states induced by positive/negative write pulses due to the absence of minority carriers in a two-terminal MFIS FTJ, which is typically neglected in previous FTJ models; iii) write-aware design space exploration for memory and analog synapse applications, which is beyond the capability of existing FTJ models. FTJ faces challenges in low ON current and relatively small ON/OFF ratio, which can be solved by introducing FeFET. However, when scaling down the thickness of ferroelectrics (tFE) due to the requirement of higher integration density for data-intensive applications, FeFET's read memory window (MW) is also reduced. In the second work, we apply the asymmetric double gate concept to decouple the trade-off between tFE scaling and MW reduction in FeFET. I demonstrate that: i) separating read and write gates and adopting a thick read gate non-FE dielectric can amplify the read MW due to electrostatic coupling between the two gates; ii) a compact model for double-gate FeFET has been demonstrated and calibrated with the experimentally measured switching dynamics; iii) with the calibrated model, design space for a scaled tFE (3nm) and logic-compatible write voltage (1.8V) is identified, offering a possible option for tFE scaling. By applying ferroelectric device models, circuit-level studies for data-intensive tasks can be conducted. FeFET 1T NOR Array is promising for multiple applications yet not well studied on its write mechanism and schemes. In my third work, I demonstrate: i) a comprehensive model which reflects two FeFET write mechanisms – one to ground source (S), drain (D) & body (B) nodes and use the gate (G) to write, and the other to float S/D and use G & B to write; ii) 3 write schemes for conventional FeFET 1T NOR arrays and another one for the diagonal array, the latter of which shows the advantages of low write energy and high write efficiency but with the penalty area cost; iii) a study of parasitic parameters, particularly gate resistance (Rg), gate capacitance (Cg) and word line resistance (RWL), in FeFET 1T NOR array, which is critical for further prospective 1T NOR array design; iv) an implementation of FeFET 1T NOR array in the Ising machine system to evaluate the feasibility of our write scheme and array structure for embedded NVM applications. Despite FeFET's excellent read characteristics, it suffers from the retention loss caused by the internal voltage (Vint), which can be solved by introducing 1 transistor-1 capacitor (1T1C) FeRAM. However, due to the destructive read operation of conventional 1T1C FeRAM, the requirement of endurance cycles is nontrivial. As a result, I exploit the quasi-nondestructive readout (QNRO) 2 transistors-n capacitors (2T-nC) FeRAM to demonstrate comparative advantages in scalability, reliability, and feasibility of dense 3D integration and operation. In the last work, I show that: i) the sensing and scalability issues of conventional 1T1C FeRAM rooted in its charge-based sensing; ii) 1T1C ferroelectric metal field-effect transistor (FeMFET) suffers from poor reliability and scaling challenges; iii) the 2T-nC structure can be exploited to address their issues in scalability, density, and reliability; iv) through comprehensive experimental and theoretical studies, the design space of 2T-nC devices is explored; v) the integration and operation of 2T-nC FeRAM arrays in 2D and 3D configurations are investigated, demonstrating their potential for improved density and operation.