Plasma enhanced atomic layer deposition ZnO thin film transistors for large area circuit applications

Open Access
Li, Yuanyuan
Graduate Program:
Electrical Engineering
Doctor of Philosophy
Document Type:
Date of Defense:
May 24, 2013
Committee Members:
  • Thomas Nelson Jackson, Dissertation Advisor
  • Thomas Nelson Jackson, Committee Chair
  • Suman Datta, Committee Member
  • Jerzy Ruzyllo, Committee Member
  • Mark William Horn, Committee Member
  • ZnO thin film transistors
  • Plasma enhanced atomic layer deposition
  • hybrid CMOS
  • low-voltage operation circuits
  • tri-layer TFTs
This thesis investigates approaches for robust, high-performance thin film transistor (TFT) technology for use in large area electronic applications. The focus of the work is on oxide semiconductor TFTs and specifically ZnO TFTs. In previous work, this research group demonstrated high mobility (> 20 cm2/V•s) ZnO thin film transistors (TFTs) and fast circuits on glass and flexible polymeric substrates at 200 °C using weak oxidant plasma enhanced atomic layer deposition (PEALD). This thesis extends this foundation to hybrid inorganic/organic circuits with ink-jet printed organic semiconductor TFTs that can provide high-gain analog circuits, double-gate ZnO TFTs that can provide high-gain enhancement/depletion mode amplifiers and low operation voltage circuits, and ZnO TFTs and circuits fabricated using a tri-layer dielectric-semiconductor-dielectric deposition approach with near-zero turn-on voltage, and improved device passivation and stability. CMOS is an important technology for both digital and analog circuits. In this thesis, an inorganic PEALD n-channel ZnO and organic ink-jet printed p-channel diF-TESADT CMOS has been developed to provide high gain for analog circuits. Ink-jet printed diF-TESADT organic thin film transistors (OTFTs) on Si substrates with a thermally grown SiO2 dielectric had field effect mobility as large as 0.4 cm2/Vs. Hybrid organic/inorganic TFT inverters had sub-pA leakage current for both high and low states, high gain (~35), and good logic level conservation. Bi-functional Al/Au contacts served for both the ZnO TFTs and the diF-TESADT OTFTs, and only 4 lithography steps and 1 ink-jet printing step were used to complete the circuits. A double-gate ZnO TFT process was developed to provide flexibility in circuit design. Compared to bottom-gate-only ZnO TFTs, double-gate ZnO TFTs have improved mobility, subthreshold slope, and bias stability. For some applications, the TFT top-gate can be used to adjust the bottom-gate turn-on and threshold voltage. This allows the logic transition point for circuits to be adjusted for low voltage operation. Using this approach, high-gain inverters (gain >100) and low-voltage ring oscillators using double-gate TFTs have been demonstrated. Double-gate inverters using a depletion mode load device have gain larger than 100. 15-stage double-gate ZnO TFT ring oscillators operate with VDD = 1.5 V, ID = 28 µA, and a propagation delay of 2 µs/stage. Finally, tri-layer PEALD ZnO TFTs were developed to provide improved stability and passivation for ZnO TFTs. Turn-on and threshold voltage shifts after passivation are common problem for oxide TFTs. Bottom-gate, top-contact tri-layer TFTs use an Al2O3-ZnO-Al2O3 tri-layer deposited in one deposition run that provides protection for the active layer back surface with no extra passivation step. Compared to conventional passivated (non-tri-layer) ZnO TFTs, these tri-layer devices have similar field effect mobility, but near zero turn-on voltage and improved bias stability. 7-stage ring oscillators operated at 100 ns/stage with a supply voltage 10 V and operated at 3.5 MHz at a supply voltage of 17 V, corresponding to a propagation delay of ~ 27 ns/stage. The developments outlined in this thesis provide a foundation for highly stable ZnO TFTs and high-gain, low operation voltage TFT circuits fabricated at low temperature.