Bottom-up and top-down fabrication of nanowire-based electronic devices: In situ doping of vapor liquid solid grown silicon nanowires and etch-dependent leakage current in InGaAs tunnel junctions

Open Access
- Author:
- Kuo, Meng-wei
- Graduate Program:
- Electrical Engineering
- Degree:
- Doctor of Philosophy
- Document Type:
- Dissertation
- Date of Defense:
- March 25, 2013
- Committee Members:
- Theresa Stellwag Mayer, Dissertation Advisor/Co-Advisor
Theresa Stellwag Mayer, Committee Chair/Co-Chair
Joan Marie Redwing, Committee Member
Suman Datta, Committee Member
Nitin Samarth, Committee Member - Keywords:
- nanowire
VLS
InGaAs
tunnel - Abstract:
- Semiconductor nanowires are important components in future nanoelectronic and optoelectronic device applications. These nanowires can be fabricated using either bottom-up or top-down methods. While bottom-up techniques can achieve higher aspect ratio at reduced dimension without having surface and sub-surface damage, uniform doping distributions with abrupt junction profiles are less challenging for top-down methods. In this dissertation, nanowires fabricated by both methods were systematically investigated to understand: (1) the in situ incorporation of boron (B) dopants in Si nanowires grown by the bottom-up vapor-liquid-solid (VLS) technique, and (2) the impact of plasma-induced etch damage on InGaAs p+-i-n+ nanowire junctions for tunnel field-effect transistors (TFETs) applications. In Chapter 2 and 3, the in situ incorporation of B in Si nanowires grown using silane (SiH4) or silicon tetrachloride (SiCl4) as the Si precursor and trimethylboron (TMB) as the p-type dopant source is investigated by I-V measurements of individual nanowires. The results from measurements using a global-back-gated test structure reveal non-uniform B doping profiles on nanowires grown from SiH4, which is due to simultaneous incorporation of B from nanowire surface and the catalyst during VLS growth. In contrast, a uniform B doping profile in both the axial and radial directions is achieved for TMB-doped Si nanowires grown using SiCl4 at high substrate temperatures. In Chapter 4, the I-V characteristics of wet- and dry-etched InGaAs p+-i-n+ junctions with different mesa geometries, orientations, and perimeter-to-area ratios are compared to evaluate the impact of the dry etch process on the junction leakage current properties. Different post-dry etch treatments, including wet etching and thermal annealing, are performed and the effectiveness of each is assessed by temperature-dependent I-V measurements. As compared to wet-etched control devices, dry-etched junctions have a significantly higher leakage current and a current kink in the reverse bias regime, which is likely due to additional trap states created by plasma-induced damage during the Cl2/Ar/H2 mesa isolation step. These states extend more than 60 nm from the mesa surface and can only be partially passivated after a thermal anneal at 350oC for 20 minutes. The evolution of the electrical properties with post-dry etch treatments indicates that the shallow and deep-level trap states resulting from ion-induced point defects, arsenic vacancies and hydrogen-dopant complexes are the primary cause of degradation in the electrical properties of the dry-etched junctions.