SELECTION ALGORITHMS FOR TRANSISTOR QUANTIZATION ADC’S BASED ON DYNAMIC PROGRAMMING
Open Access
- Author:
- Ozdemir, Ali
- Graduate Program:
- Computer Science and Engineering
- Degree:
- Doctor of Philosophy
- Document Type:
- Dissertation
- Date of Defense:
- July 03, 2020
- Committee Members:
- Kyusun Choi, Dissertation Advisor/Co-Advisor
Kyusun Choi, Committee Chair/Co-Chair
Thomas Jackson, Committee Member
Mohamed Khaled Almekkawy, Committee Member
Susan E Trolier-Mckinstry, Outside Member
Chitaranjan Das, Program Head/Chair - Keywords:
- TIQ
Flash ADC
Dynamic Programming
DNL
INL - Abstract:
- Biometrics offers an extra security layer for accessing private information and files [1–5]. Finger scanning is the most commonly used biometric technology on the market, and the robustness of the system can be further enhanced by including finger vein imaging [6–8]. High-frequency ultrasound offers better penetration depth and field of view along with enough resolution compared to other techniques for under skin imaging [9, 10]. An electronic system with a high-frequency ultrasound transducer should provide high speed [11,12] and low error under different process, voltage, and temperature (PVT) conditions. Threshold Inverter Quantization (TIQ) flash ADC is a good candidate for these systems because the digital inverter circuit provides very high speed [13,14]. Even though inverters are fast, PVT variations can cause significant sampling errors. This thesis’s main thrust is to improve the precision of TIQ flash ADC and reduce design time. The improvement is presented in the following five steps. First, previous selection algorithms in the literature are based on greedy algorithms. However, greedy algorithms do not efficiently search the solution space of a problem for the given criteria. Dynamic programming is a better approach for such optimization problems [15,16]. Therefore, a dynamic programming version of the previous approach [17] is introduced to reduce differential non-linearity (DNL) errors and is then compared to the greedy algorithm with dynamic programming. Dynamic programming returned 30% better DNL values for 6-bit ADC and 34% better DNL values for 8-bit ADC. As a result, the correct algorithm selection reduced linearity errors and achieved higher precision. Second, previous selection algorithms, [17] and [18], introduced a size relationship between comparators to reduce DNL errors under different process parameters. According to the data set, this approach can be applied when transistor widths are bigger than 20μm. However, if the transistors’ size is smaller than that, the exponential change in threshold voltages are observed on the comparators. Accordingly, size relation is removed from the program proposed in the second study. The data set is extended to reach compromise threshold voltage values of TIQ comparators under different process variations. The program returned 2.1 times smaller DNL error for 6-bit and 1.92 times smaller DNL error for 8-bit TIQ ADC design. Hence, forcing the size relationship between comparators is not a good approach when sizes get smaller. Extending data sets with the penalty of data creation time is a better approach. Third, the second study’s proposed algorithm has a long-running time and extensive memory usage because of the implemented precision on DNL calculation. The precision of execution is relaxed by using the same least significant bit (LSB) value to calculate DNL error for all the comparators in the third study. This relaxation leads to reduced running time and memory usage. In order to recover precision, DNL errors are re-calculated at the end of the program. Furthermore, the data set is extended by adding threshold voltages on supply voltage variation and temperature variation for total DNL improvement under different PVT variation cases. Consequently, DNL error decreased from 0.0327 to 0.0249 for 6-bit and from 0.0602 to 0.0299 for an 8-bit TIQ flash ADC design. Moreover, the running time of the program decreased from 14 hours to 6 hours for a 6-bit design. To conclude, voltage and temperature variations are included in the selection algorithm, and running time is reduced with an approximation for the DNL calculation. Fourth, since integral non-linearity (INL) error can cause precision losses like DNL error, it is crucial to decrease it. Therefore, the previously obtained comparator selection procedure in the third study is updated to reduce DNL and INL errors simultaneously. As a result, a 6-bit TIQ ADC design with the 0.0925 DNL, 0.2688 INL, and 8-bit TIQ ADC with 0.15 DNL and 1.22 INL errors is achieved. The minimum INL error with the current data set for 6-bit is 0.257, and 1.16 for 8-bit with the DNL error of 1. As a result, a program with simultaneous DNL-INL optimization is introduced, and INL errors are improved by trading-off some DNL error in comparison to the third study. Fifth, creating a data set of the selection algorithm using Hspice takes more than 150 days for new technologies or vendors. If approximate data with a small margin of error can be created, the time to design TIQ ADC with new technologies can be reduced. Therefore, supervised learning with the ordinary least square (OLS) technique is used to create the data set in under 15 minutes rather than 150 days. Further, an 8-bit TIQ flash ADC with 0.235 DNL, and 2.345 INL error is achieved with the approximate data set. In conclusion, the overall design time of TIQ flash ADC decreased from months to hours for different technologies. Threshold inverter quantization comparator is fast, low power, and easy to design compared to a differential input voltage comparator. On the other hand, it is more susceptible to process, voltage, and temperature variation. This thesis improves the resilience of TIQ flash ADC against these variations by using dynamic programming and optimizes differential and integral non-linearity errors.