Assuring Security and Privacy of Emerging Non-Volatile Memories
Open Access
- Author:
- Khan, Mohammad Nasim
- Graduate Program:
- Electrical Engineering
- Degree:
- Doctor of Philosophy
- Document Type:
- Dissertation
- Date of Defense:
- November 15, 2019
- Committee Members:
- Swaroop Ghosh, Dissertation Advisor/Co-Advisor
Mehdi Kiani, Committee Member
Vishal Monga, Committee Member
Trent Ray Jaeger, Committee Member
Saptarshi Das, Outside Member
Kultegin Aydin, Program Head/Chair
Swaroop Ghosh, Committee Chair/Co-Chair - Keywords:
- Non-Volatile Memory
NVM
Security
Privacy
Reliability
Testing
STTRAM
RRAM
PCM
MRAM
FeRAM - Abstract:
- At the end of Silicon roadmap, keeping the leakage power in tolerable limit has become one of the biggest challenges. Several promising Non-Volatile Memories (NVMs) such as, Spin-Transfer Torque RAM (STTRAM), Magnetic RAM (MRAM), Phase Change Memory (PCM), Resistive RAM (RRAM) and Ferroelectric RAM (FeRAM) are being investigated to address the issue since they offer high density and consumes zero leakage power. On one hand, the above desired properties of emerging NVMs make them suitable candidates to several applications including replacing conventional memories. On the other hand, their unique characteristics such as, high and asymmetric read/write current and persistence bring new threats to data security and privacy. Some of these memories are already deployed in full systems and as discrete chips and are believed to become ubiquitous in future computing devices. Therefore, it is utmost important to investigate their security and privacy issues. Note that these NVMs can be considered for cache, main memory or storage application. They are also suitable to implement in-memory computation which increases system throughput and eliminates Von- Neumann Bottleneck. Compute-capable NVMs imposes new security and privacy challenges that are fundamentally different that their storage counterpart. This work identifies NVM vulnerabilities, attack vectors originating from device level all the way to circuit and system point of view considering both storage and compute applications. It also summarizes the circuit/system level countermeasures to make the NVMs robust against security and privacy issues. NVMs also suffer from new reliability issues that can be leveraged by an adversary to launch various attacks. Therefore, test techniques are required to capture reliability issues during testing phase and discard the chip. This work also proposes test techniques that can capture reliability issues in short test time.