Investigating Alternative Sacrificial Channel Materials for Grow-in-place Encapsulated Silicon Nanowires

Open Access
Author:
Al Balushi, Zakaria Yahya
Graduate Program:
Engineering Science
Degree:
Master of Science
Document Type:
Master Thesis
Date of Defense:
November 16, 2012
Committee Members:
  • Stephen Joseph Fonash, Thesis Advisor
  • Mark William Horn, Thesis Advisor
  • Wook Jun Nam, Thesis Advisor
Keywords:
  • grow-in-place nanowire silicon sacrificial nanochannel
Abstract:
Nanowires have become of great interest for many applications in different fields of science and engineering. They have many interesting properties, such as high surface area to volume ratios and tunable electrical properties. These properties make nanowires ideal for integration into electronic and optoelectronic high performance devices. Nanowire-based logic devices are still in an embryonic stage and more research is needed for the integration of nanowire building blocks into CMOS technology. For the potential future of semiconductor nanowires in very-large-scale-integrated VLSI circuits, the challenge of high density alignment and precise placement of nanowires for individual device control must be addressed. The “Grow-in-Place” approach for encapsulated nanowires can overcome some of the limitation of post-growth integration of these one-dimensional materials by essentially combining growth and integration into a single step. In order to build robust nanowire FETs, precise control over the in-plan growth of the nanowires must be realized. The grow-in-place approach can provide an excellent platform for innovative nanowire based TFTs. This thesis is intended to investigate alternative sacrificial materials to fabricate nanochannels for in-plane growth of encapsulated SiNWs using the grow-in-place approach. The objective is to advance the current grow-in-place approach that has been proposed by the Fonash Research Group. This keen interest in optimizing the approach is important in order to make encapsulated growth of SiNWs commercially feasible and economical for high volumetric device integration of nanowire FETs that will enhance the performance of current CMOS technology.