Crossbar arrays using emerging Non-Volatile Memory (NVM) technologies such as Resistive RAM (ReRAM) offer high density, fast access speed, and low-power. However, the bandwidth of the crossbar is limited to single-bit read/write per access to avoid selection of undesirable bits. We propose a technique to perform multi-bit read and write in a Diode-STTRAM (Spin-Transfer Torque RAM) crossbar array. The simulation shows that the biasing voltage of half-selected cells can be adjusted to improve the sense margin during read which reduces the sneak path current through the half-selected cells. During write operation, the half-selected cells are biased with a pulse voltage source which increases the write latency of these cells and enables to write 2-bits while keeping the half-selected bits undisturbed. Simulation results indicate that biasing the half-selected cells by 700mV can enable reading as much as 512-bits while sustaining 512x512 crossbar with 2.04 years retention. The 2-bit write operation requires pulsing by 50mV to optimize write energy.
