LOW POWER, SECURE AND ROBUST DESIGNS OF NON-VOLATILE MEMORIES
Open Access
- Author:
- Motaman, Seyedhamidreza
- Graduate Program:
- Computer Science and Engineering
- Degree:
- Doctor of Philosophy
- Document Type:
- Dissertation
- Date of Defense:
- September 27, 2018
- Committee Members:
- Swaroop Ghosh, Dissertation Advisor/Co-Advisor
Swaroop Ghosh, Committee Chair/Co-Chair
Mahmut Taylan Kandemir, Committee Member
Mehdi Kiani, Committee Member
Saptarshi Das, Outside Member - Keywords:
- STTRAM
Sense Margin
MTJ
Slope Sensing
Process Variation
Voltage Boosting
Voltage Feedback
Self-Reference
Destructive Sensing
Domain wall memory
shift power
cache segregation
dynamic shift current modulation
dynamic write current modulation
cross-layer design
synergistic systems
Dynamic shift current modulation
Dynamic write current modulation
Variation tolerant design
Resistive RAM
computing in memory
Crossbar Array.
Data security
magnetic attack
cache bypass
checkpointing. - Abstract:
- In the last few decades, computation power has been increasing, thanks to CMOS scaling, which in turn results in growing demand for high-density memories to meet the large bandwidth requirement. However, CMOS scaling is approaching the end of roadmap and it is experiencing significant challenges such as high power-density, process variation, high standby power, and reliability issues. In addition, the increasing demand for high performance computing (HPC) and integration of multiple cores on a single die have widened the speed gap between logic and memory, that is known as the “memory-wall”. Process variability and standby power are posing severe obstruction towards SRAM/DRAM scaling to future nodes. On one hand, industry and academia began investigating alternative memory technologies, such as Spin-Torque Transfer RAM (STT-RAM), Domain Wall memory (DWM), Phase-Change RAM (PCRAM), Ferro-electric RAM (FeRAM), Resistive RAM (RRAM), and Magnetic RAM (MRAM). These emerging non-volatile memory technologies offer the speed of SRAM, the high density of DRAM, and the non-volatility of Flash memory. On the other hand, the speed gap between the processor and memory impedes the continuous performance improvement of the traditional von Neumann architecture. In order to address this challenge, extensive amount of research is performed to explore the alternative non-von Neumann architectures based on the concept of computing in memory. Among these memories, spintronic memories (i.e. STTRAM, DWM) have proven to be potential alternatives to replace on-chip SRAM owing to their remarkable high density, zero standby power, high speed, high endurance and CMOS compatibility. Nevertheless, STTRAM suffers from crucial challenges such as high write energy, long write time and poor sense margin. Furthermore, it suffers from process variation induced write latency and write power degradation. Moreover, the sensitivity of magnets to ambient parameters and data persistence makes the spintronic memories vulnerable to tampering and data leakage. In addition to the aforementioned challenges associated with STTRAM, DWM suffers from shift latency and shift power overhead, aspect ratio mismatch, and segregated read and write heads. The recent experimental studies have revealed that RRAM is a promising alternative to implement main memory due to their small footprint and zero standby power. Therefore, realizing logic operations within RRAM crossbar arrays is a promising approach to implement computing-in-memory systems. However, RRAM crossbar array suffers from sneak-path problem which leads to poor sense margin, higher power consumption, and limited array size. In the first part of this thesis, we propose the circuit and architectural techniques to improve read yield, write latency, write power and data security of STTRAM. We introduce slope sensing, a destructive sensing technique for elimination of the reference resistance variation in order to enhance read yield of STTRAM arrays. Further, we propose a non-destructive sensing scheme which exploits a voltage feedback and boosting (VFAB) approach to develop large sense margin and substantially reduce sensing power. We introduce a novel and adaptive write current boosting to mitigate process variation induced write latency and write power degradation. In this technique, the bits experiencing worst-case write latency are fixed through write current boosting. Next, we investigate data security of STTRAM last level cache under magnetic attack where we apply low-overhead micro-architecture methods to avoid errors in presence of the magnetic attack. In the second part of this thesis, we propose circuit and architectural techniques to overcome the design challenges associated with DWM. We apply layout techniques such as sharing of diffusion, bitlines and shift lines in order to enhance bitcell density. Circuit methods such as merged read-write head for improvement of bitcell density and shift gating to reduce shift power are proposed. Furthermore, we apply the micro-architecture techniques such as cache segregation using a novel replacement policy as well as dynamic current boosting based on workload monitoring in order to mitigate shift power and shift latency. Moreover, adaptive write and shift current boosting is proposed to mitigate process variation induced performance and power degradation. Lastly, we propose a low-power dynamic computing in memory system which can implement various functions in the Sum of Product (SoP) form in RRAM crossbar array architecture. This technique benefits from the nonlinear characteristic of a selector diode for improvement of the sense margin in order to implement higher fan-in logic gates.