2D ELECTROSTRICTIVE FET BASED CIRCUITS: COMPACT MODELING AND DEVICE-CIRCUIT CO-DESIGN

Thakuria, Niharika

2D ELECTROSTRICTIVE FET BASED CIRCUITS: COMPACT MODELING AND DEVICE-CIRCUIT CO-DESIGN

Open Access

Author:

Thakuria, Niharika

Graduate Program:

Electrical Engineering

Degree:

Master of Science

Document Type:

Master Thesis

Date of Defense:

December 08, 2017

Committee Members:

Sumeet Kr. Gupta, Thesis Advisor
Swaroop Ghosh, Committee Member
Saptarshi Das, Committee Member

Keywords:

2D FET
bandgap modulation
memory
piezoelectric
SRAM
steep switching

Abstract:

2D Electrostrictive FET (EFET) is an emerging steep switching device with immense potential to replace conventional MOSFETs. EFET has 4-terminals: gate (G), source (S), drain (D) and back contact (B). An electrostrictive material (EM) is sandwiched between gate and back contact of the EFET. EM exhibits longitudinal expansion on application of voltage (VGB) across it inducing pressure on 2D channel material. This results in bandgap modulation and its steep switching (sub 60mV/dec) characteristics. In this work, we present a Verilog A based compact model of EFET that solves the governing equations of electrostrictive effect and 2D electrostatics/channel transport self-consistently. With this model we perform simulations of EFET device characteristics and EFET based circuits (using HSPICE). We observe 163% increase in ON current and 9% decrease in sub threshold swing (SS) in EFET compared to 2D FET. By virtue of its unique operating mechanism and structure, EFET presents several opportunities for optimization. We show that band-bending (hence EFET device characteristics) can be effectively optimized through: (i) Strain Transduction Coefficient (STC which is related to electrostrictive and 2D material) and (ii) back voltage (VB). We show 42% decrease in SS and 7.5X increase in ION by increasing STC=2856 eV-pm/V (70% transduction efficiency). In addition, by modulating VB=-0.6V, ION increases by 2.8X. The steep switching and greater drive strength of EFETs is accompanied by capacitance overheads due to - (i) electrostrictive dielectric (CGB) and (ii) parasitic capacitance (CGD, CGS). A potential outcome of this is higher delay in EFET circuits. Our study shows the possibility of enhancement in performance/stability/energy efficiency of EFET circuits by co-optimization of STC and VB of EFETs. Precisely, this work focuses on thorough analysis and device-circuit co-optimization of the following EFET based circuits: (i) ring oscillator (RO) and (ii) SRAM. Through transient analysis of 7-stage EFET based ring oscillator (RO) we investigate the influence of capacitance driven delay in EFET circuits compared to 2D FET circuits. Firstly, we study energy-delay in RO with ideal 2D/EFET (ignoring parasitic capacitances: CGB/CGD/S). We observe 1.15X lower delay than the 2D FET RO at iso-energy. Parasitic capacitances (CGB/CGD/S) considered, EFET RO performs 1.2X slower than 2D FET RO at iso-energy. Increased delay is result of large CGD/S overlap capacitances (higher than CGD/S in 2D FET) in preliminary EFET structure (EFET 1). To improve energy-delay performance, we propose EFET 2 with CGD/S comparable to 2D FET. However, EFET 2 RO shows 2.26X larger delay compared to 2D FET RO due to inherent CGB. STC optimization of EFET 2 RO helps achieve 1.7X lower energy at iso-delay (at 70% transduction efficiency). We also note that the EFET 2 RO shows energy-delay benefits over 2D FET RO in wire capacitance dominated (Cw>2fF) circuits. Finally, we study EFET based SRAMs with (i) EFET as drop-in replacement (EFET SRAM-I) and (ii) EFET with separate VB for access transistor (EFET SRAM-II). Based on our initial device analysis with STC and VB, we propose EFET SRAM-II since this design permits their co-optimization. Analysis of SRAM-I and SRAM-II are carried out individually for EFET 1 and EFET 2. First, we compare EFET 1 SRAM-I with EFET 2 SRAM-I. We conclude better performance characteristics of the latter which we summarize as: 15% lower read time at comparable read stability and 3% decrease in write time (compared to 2D FET SRAM). STC optimization of EFET 2 SRAM-I leads to 50% decrease in read time, 33% increase in noise margin and 6% decrease in write time (compared to 2D FET SRAM) at 70% transduction efficiency. Applying VB and STC co-optimization in EFET SRAM-II, both EFET 1 and EFET 2 based configurations display drastic improvements. 20% and 70% increase in read noise margin is observed at STC=2856 eV-pm/V (70% efficiency) with VB=0V for EFET 1 SRAM-II and EFET 2 SRAM-II respectively. With VB=0.6V and STC=2856 eV-pm/V, 30% and 50% reduction in write is seen in EFET 1 SRAM-I and EFET 2 SRAM-II respectively.