DEVICE CIRCUIT ANALYSIS OF FERROELECTRIC FETs FOR LOW POWER LOGIC & MEMORIES

Open Access
- Author:
- Gupta, Shreya
- Graduate Program:
- Electrical Engineering
- Degree:
- Master of Science
- Document Type:
- Master Thesis
- Date of Defense:
- August 03, 2017
- Committee Members:
- Sumeet Kumar Gupta, Thesis Advisor/Co-Advisor
Mehdi Kiani, Committee Member - Keywords:
- Ferroelectric FETs
Hysteresis
Negative Capacitance
Negative Differential Resistance
Static Random Access Memories (SRAMs) - Abstract:
- Ferroelectric FETs (FEFETs) are emerging devices with an immense potential to replace conventional MOSFETs by virtue of their steep switching characteristics. The ferroelectric (FE) material in the gate stack of the FEFET exhibits negative capacitance resulting in voltage step up action which entails sub-60mV/decade sub-threshold swing at room temperature. The thickness of the FE layer (T¬¬FE) is an important design parameter, governing the device-circuit operation. This thesis extensively analyzes the impact of TFE on the characteristics of FEFET devices and circuits and presents important design insights for logic and SRAM design. While it is well known that increasing T¬¬FE yields higher gain albeit with the possibilities of introducing hysteresis, our analysis points to other unconventional effects arising from TFE optimization. Depending on the attributes of the underlying transistor, increasing TFE beyond a certain value may lead to loss in saturation and/or negative differential resistance in the output characteristics. While the former effect results in the loss in gain of a logic gate, the latter yields hysteretic voltage transfer characteristics. We also discuss the effect of T¬¬FE on the inherent polarization lag in the FE with respect to the applied voltage and its important consequences on the circuit performance. We show that for high TFE, the delay of the circuit may increase with an increase in supply voltage. We also observe that SRAMs based on FEFETs show better performance in terms of access time and read/hold stabilities but at the cost of higher write time. All these factors need to be considered while optimizing TFE for logic and memory applications. With proper TFE optimization, FEFETs show an immense promise yielding 25% lower energy at iso-delay for supply voltages < 0.25 V. SRAMs based on FEFET show 5%–12% larger read stability and 9%–26% lower access time, albeit with an increase in the write time.