A Low Power and Area Efficient CMOS Implementation of Multilayer Feedforward Artificial Neural Network

Restricted (Penn State Only)
Patki, Mayuresh Premanand
Graduate Program:
Electrical Engineering
Master of Science
Document Type:
Master Thesis
Date of Defense:
August 04, 2017
Committee Members:
  • Seth Wolpert, Thesis Advisor
  • Scott Von Tonningen, Committee Member
  • Wolfram Bettermann, Committee Member
  • Artificial Intelligence
  • Artificial Neural Networks
  • Metal Oxide Semiconductor Implementation Service
  • Integrated Circuit
  • CMOS
  • Very Large Scale Integration
  • McCulloch and Pitts neuron
  • Perceptron
  • Backpropagation Algorithm
  • Synapses
  • Gilbert Multiplier Cell
  • Activation Function Circuit
  • Floating Gate
  • Single Transistor Learning Synapse
  • Post-Synaptic Current
  • Spike Timing Dependent Plasticity
  • Long Term Potentiation
  • Long Term Depression
  • Static Random Access Memory
  • Memristor
  • Mean Square Error
  • Cadence OrCAD Capture
  • Cadence PSpice A/D
  • Electric VLSI Design System
  • Network Consistency Check
  • Layout Vs Schematic Check
  • XOR Classification Problem
  • Time Domain
  • Instantaneous Power Dissipation
  • Loading
  • Learning Rate
  • Mixed Signal
  • System on Chip
  • Field Programmable Gate Arrays
With several advancements in medical science being carried out over the past few decades, there has been a constant need to process information artificially, the way it is processed inside the human body. This inherent attribute of Artificial Intelligence (AI) is achieved in practice using Artificial Neural Networks (ANNs). ANNs have been around since 1943 and used since then for artificial information processing and neural computation. This thesis focuses on the hardware implementation of an artificial neural network using CMOS technology. The design is carried out in the analog domain to exploit certain advantages of analog integrated circuit design, such as, high efficiency, in terms of area and power, and ease of computation. The neural architecture designed is a multilayer feedforward neural network to solve the XOR classification problem, which serves as a benchmark for several complex classification problems that are not linearly separable. Each component circuit of the network, such as the synapse circuit that performs the multiplication operation and the non-linear activation function circuit that acts as squashing function, is designed using MOSFETs operating in the sub-threshold (weak inversion) region. The schematic designs are carried out using Cadence OrCAD Capture version 16.6 EDA software and simulated using PSPICE version 16.6, an in-built simulation tool within OrCAD capture. The layout of the individual components and the overall schematic is also done using Electric VLSI Design software version 9.06 on a 200 nm design scale. A consistency check is carried out to ensure equivalency of layout with the schematic, for a potential scope towards chip fabrication using Metal Oxide Semiconductor Implementation Service (MOSIS) foundry. The layout of the proposed neural architecture is found to occupy an area of 0.065 〖mm〗^2, indicating design compactness to a moderate level.