Ohmic contacts to compound semiconductor transistors

Open Access
Author:
Dormaier, Robert A
Graduate Program:
Materials Science and Engineering
Degree:
Doctor of Philosophy
Document Type:
Dissertation
Date of Defense:
August 05, 2011
Committee Members:
  • Suzanne E Mohney, Dissertation Advisor
  • Suzanne E Mohney, Committee Chair
  • Joan Marie Redwing, Committee Member
  • Patrick M Lenahan, Committee Member
  • Michael T Lanagan, Committee Member
Keywords:
  • high electron mobility transistor
  • heterojunction bipolar transistor
  • surface preparation
  • indium arsenide
  • Indium gallium arsenide
  • Ohmic contacts
  • antimonide based compound semiconductor
Abstract:
This thesis addresses Ohmic contacts to InAlSb/InAs high electron mobility transistor (HEMT) heterostructures and InGaAs epilayers. Palladium-based contacts provide very low contact resistance to both materials, which helps minimize parasitic resistances in transistors. For Pd/Pt/Au and Pd/Ru/Au contacts to the HEMTs, lower contact resistances are correlated with increasing reaction between Pd (and Pt) and the semiconductor during annealing and aging at 175–200 °C for 3 h or 1 week. Voids form in the Pt diffusion barrier layer when Pd/Pt/Au contacts are aged 1 week at 175 °C and grow larger during aging at higher temperatures. The increase in contact resistance of Pd/Pt/Au contacts by more than a factor of 2 after a 1 week, 225 °C aging cycle is discussed in light of the interfacial reactions that occur during aging. Alternatively, no reaction is observed between the Ru diffusion barrier and the semiconductor in Pd/Ru/Au contacts, which yield a contact resistance of 0.05 ± 0.01 &#937; mm after a 1 week, 225 °C aging cycle that is comparable to the minimum value of 0.03 ± 0.01 &#937; mm yielded by Pd/Pt/Au contacts. Measurement artifacts associated with the transfer length method are identified and probe placements that mitigate the artifacts are used to reliably examine low specific contact resistance (&#961;<sub>c</sub>) Ohmic contacts to InGaAs. Standardization of surface preparation procedures and a low relative humidity processing environment yield very low &#961;<sub>c</sub> contacts to n-InGaAs. Examinations of wet etchants for oxide removal after UV/O<sub>3</sub> treatment demonstrate that BOE- and NH<sub>4</sub>OH-based etchants yield much lower &#961;<sub>c</sub> values than HCl (5.0±0.6x10<sup>-9</sup> and 5.7±1.4x10<sup>-9</sup> versus 1.7±0.1x10<sup>-8</sup> &#937; cm<sup>2</sup>). Palladium and Pt yield lower as-deposited and annealed &#961;<sub>c</sub> values than Mo-, Ti-, and TiW-based contacts. Furthermore, collimated sputter-deposited contacts yield lower &#961;<sub>c</sub> values than electron-beam evaporated contacts. Several phenomena that may be responsible for the low &#961;<sub>c</sub> values of Pd-based contacts are proposed and discussed. Ohmic contacts to p-InGaAs with a thin n-InGaAs cap are also examined: Pd/Ti multilayer contacts yield &#961;<sub>c</sub> < 1x10<sup>-8</sup> &#937; cm<sup>2</sup> after 2 hr at 270 °C.