Strain engineering for strained p-channel Non-planar Tri-Gate field effect transistors

Open Access
Author:
Mujumdar, Salil Shashikant
Graduate Program:
Electrical Engineering
Degree:
Master of Science
Document Type:
Master Thesis
Date of Defense:
None
Committee Members:
  • Suman Datta, Thesis Advisor
Keywords:
  • Si
  • Embedded S/D
  • Uniaxial strain
  • Tri-gate
  • P-channel
  • SiGe
  • Gate nesting
  • Mobility enhancements
  • Fin nesting.
Abstract:
In this thesis the optimization of embedded source/drain (eS/D) shape profiles and device layouts for the 22nm node compressively strained P-channel tri-gate field effect transistors (FETs) is investigated using finite element method (FEM) simulations. Three device layout strategies namely 1) Nested fin layout 2) Nested gate layout and 3) Double nested layout were studied and the nested gate layout was found to introduce the maximum channel stress of all three. Out of the three eS/D shape profiles namely 1) Rounded eS/D 2) Sigma eS/D and 3) Square eS/D, square shaped S/D regions are found to induce maximum channel stress due to minimum average source to drain distance making them the best candidates for nested tri-gate transistors contrary to the planar case. Strained silicon-germanium (SiGe) FETs being a potential candidate for future technology nodes, a comparison between Si and Si0.4Ge0.6 with Si0.6Ge0.4/Ge eS/D P-channel tri-gate FETs for the nested gate (5 tri-gates) based on average channel stress and corresponding mobility enhancements is discussed. Superior mobility enhancement of strained Si0.4Ge0.6 channel compared to strained Si channel offsets the disadvantage of the Si0.4Ge0.6 channel stress being slightly less than the Si channel. The evolution of the channel stress following S/D recess etch and eS/D re-growth for uniaxially strained SiGe fins obtained via global strain is also investigated to evaluate the maximum achievable stress levels for a combination of globally and locally induced uniaxial strain. The eS/D stressor technique is expected to remain an important technique especially in the face of channel strain relaxation following S/D ion implantation for extremely scaled P-channel tri-gate FETs with globally induced channel strain.