Fabrication and Characterization of Semiconducting Nanowires for Tunnel Field Effect Transistors

Open Access
Vallett, Aaron Lee
Graduate Program:
Electrical Engineering
Doctor of Philosophy
Document Type:
Date of Defense:
January 07, 2011
Committee Members:
  • Theresa Stellwag Mayer, Dissertation Advisor
  • Theresa Stellwag Mayer, Committee Chair
  • Joan Marie Redwing, Committee Member
  • Suman Datta, Committee Member
  • Jun Zhu, Committee Member
  • TFET
  • tunnel FET
  • VLS Si nanowire
  • axial doping profile
  • scanning capacitance microscopy
  • SCM
  • InGaAs nanowire
  • variable temperature I-V
The scaling of traditional metal-oxide-semiconductor field-effect transistors (MOSFETs) is hitting a limit, not due to difficulties in fabricating short gate lengths, but rather to an ongoing power crisis. As channel lengths have been reduced power densities of integrated circuits have risen dramatically. While supply voltage scaling would alleviate many power concerns, the MOSFET structure fundamentally limits the amount that voltages can be reduced. Because MOSFET operation is governed by thermal emission of carriers over a potential barrier, the subthreshold swing from the off to on current is limited to a minimum of 60 mV/decade of current. Therefore, reductions in the supply voltage will degrade the on/off current ratio. The tunnel field-effect transistor (TFET) has emerged as a potential solution to these problems. Current is controlled by band-to-band tunneling through a barrier that is modulated by the gate, and subthreshold swings below 60 mV/dec. can be achieved. While TFET simulations are quite promising, subthreshold swings below 60 mV/dec. at technically relevant on-currents have yet to be demonstrated experimentally. Nanowire geometries and III-V semiconductor channel materials are predicted to improve TFET performance by increasing gate control and tunneling current. In this dissertation the fabrication of TFETs from semiconducting nanowires will be investigated. First, axially doped silicon (Si) nanowire in situ p-n junctions will be studied. By controlling the nanowire growth, separate p and n-type segments can be formed to create a rectifying junction. While as-grown nanowire junctions do not have the abruptness necessary to facilitate band-to-band tunneling, thermally oxidized nanowires are shown to have a p-n-n+ profile with an abrupt n-n+ junction. By gating the nanowires an abrupt electrostatically-doped p+-n+ junction can be formed that permits reverse-biased tunneling. These p-n-n+ nanowires will be integrated into a top-gated lateral TFET test structure. Current-voltage (I-V) measurements will show that the gate-controlled tunneling current is composed of both direct band-to-band tunneling and trap-assisted tunneling components. Finally, p+-n+ and p+-i-n+ InGaAs nanowires with abrupt, heavily doped junctions will be etched from a planar wafer grown by molecular beam epitaxy (MBE). The nanowires will be integrated into a lateral test structure, and characterized by I-V measurements. These results will show that surface conduction is a strong component of device operation, but that it can be reduced by thermal annealing. TFETs will be fabricated from the p+-i-n+ nanowires, and gate-controlled Esaki diode characteristics will be observed. While elevated surface leakage current will limit the device performance, the Esaki characteristics will indicate that band-to-band tunneling can be induced in a nanowire TFET. The platforms and analysis developed in this dissertation will permit advanced studies of semiconducting nanowire TFETs.