Investigating the properties of Silicon Nanowires synthesized via Grow-in-place Approach

Open Access
- Author:
- Garg, Pranav
- Graduate Program:
- Engineering Science and Mechanics
- Degree:
- Doctor of Philosophy
- Document Type:
- Dissertation
- Date of Defense:
- July 12, 2010
- Committee Members:
- Stephen Joseph Fonash, Dissertation Advisor/Co-Advisor
Stephen Joseph Fonash, Committee Chair/Co-Chair
Dr Sanjay Joshi, Committee Member
Samia A Suliman, Committee Member
Jun Huang, Committee Member - Keywords:
- VLS growth
Silicon nanowires
unintentional doping
AMOSFETs - Abstract:
- In recent year, silicon nanowires (SiNWs) have become the subject of intense research activity due to their potential as building blocks for future generation of nanoelectronic devices. These SiNWs are typically synthesized using the gold-catalyzed vapor-liquid-solid (VLS) growth mechanism. However, for SiNW device fabrication, a number of post-growth processing steps are required, such as collecting/harvesting the nanowires from the growth substrate, transferring them and manipulating/assembling the nanowires on another substrate for device fabrication. As a result, such ‘grow-and-place’ approaches to SiNW device fabrication typically suffer from low yields, contamination issues, and overall complexity of the process. The nano-tunnel template ‘grow-in-place’ approach recently demonstrated by our group provides a unique and very convenient methodology for SiNW synthesis and nanowire device fabrication. In this approach, a nano-tunnel template guides the nanowire growth and provides control on the dimensions and position of the nanowire, thereby eliminating the need for any post-growth nanowire manipulation/assembly steps. Two different versions of the nano-tunnel template approach were investigated in this study, one in which the nanowires are allowed to grow without any confinement outside the template (i.e. the extruded SiNW growth approach) and the other in which the nanowires are allowed to grown confined inside the template (i.e. the encapsulated SiNW growth approach). This study investigates the basic electrical properties of the nanowires and/or the nanowire devices fabricated using these grow-in-place approaches. The extruded SiNW approach, while not allowing us precise control on nanowire dimension and position, is well suited for investigating the basic electrical properties of VLS-grown SiNWs. We have used this approach to characterize the resistivity of VLS-grown SiNWs, and have identified how the presence of residual gold catalyst incorporated into the nanowire can lead to the observed ‘unintentional’ p-type doping in the gold-catalyzed VLS-grown SiNWs. The extruded SiNW approach was also used to further explore accumulation-mode (AMOSFET) devices. The impact of source/drain contact resistance, as well as influence of annealing on AMOSFET transfer characteristics has been investigated. The properties (ION/IOFF ratios, subthreshold swing) of AMOSFETs fabricated in this study were found to be comparable with the best reported values for SiNW FETs in literature. AMOSFETs were also fabricated on intentionally doped SiNWs in an attempt to improve AMOSFET performance; however, these devices exhibited very poor transfer characteristics. Reasons for this observation and possible solutions are discussed in this work. The encapsulated SiNW approach was explored in this study as a means to synthesize arrays of SiNWs with precise control on dimensions and position of the nanowires, and fabricated devices on them. While we succeeded in synthesizing arrays of precisely controlled SiNWs, the devices fabricated on encapsulated SiNWs exhibited very poor transfer characteristics due to the very high resistance of the encapsulated SiNWs. Moreover, the surface of the encapsulated SiNWs was found to be very rough, and presence of voids/pores was also observed in some SiNWs. Some possible solutions to these issues are discussed in this work.