Silicon Nanowire Field Effect Devices
Open Access
- Author:
- Ho, Tsung ta
- Graduate Program:
- Electrical Engineering
- Degree:
- Doctor of Philosophy
- Document Type:
- Dissertation
- Date of Defense:
- July 21, 2009
- Committee Members:
- Theresa Stellwag Mayer, Dissertation Advisor/Co-Advisor
Theresa Stellwag Mayer, Committee Chair/Co-Chair
Joan Marie Redwing, Committee Member
Suzanne E Mohney, Committee Member
Jerzy Ruzyllo, Committee Member - Keywords:
- VLS
silicon nanowire
MOSFET - Abstract:
- This dissertation presents research that studied the electrical properties of vapor-liquid-solid grown silicon nanowires by developing robust device integration processes and methods to characterize the resulting devices. Silicon nanowire in situ p-type and n-type doping and thermal oxidation were first investigated as they are essential processes required for device integration. The doping efficiency of phosphine, diborane and trimethylboron were studied using a global-back-gate four-point resistance test structure. The results of the resistivity measured for different dopant to source gas flow ratios provide the conditions for the vapor-liquid-solid growth of axial modulation doped p- and n-type silicon nanowires segments needed for device engineering. Investigation of silicon nanowire thermal oxidation shows that the nanowire oxide shell growth rate is significantly affected by stress due to its convex surface. Fabrication processes were developed for the integration of non-self-aligned top-gate field effect devices using uniformly-doped thermally-oxidized silicon nanowires that require lower gate voltage swing to turn the transistor on and off and have reduced hysteresis compared to global-back-gate devices. Field effect properties of the top gate devices were investigated and show that carrier transport is impeded by the Schottky barrier source/drain contacts. The global back gate was used to electrostatically dope the exposed source/drain segements to enhance the carrier tunneling through the Schottky barrier and to increase the on-state current. In addition, because the top gate electric field does not affect the Schottky barrier source/drain region, the interface state density is extracted from inverse subthreshold slope, providing direct insight into this parameter that significantly affects the transport properties of nanowire field effect devices. Synthesis and structural properties of in situ axially-doped n+-p--n+ silicon nanowires were then studied by integrating silicon nanowires with two heavily-doped end (source/drain) segments and a lightly-doped middle (body) segment. This device structure overcomes the large Schottky-barrier-induced contact resistance and source/drain series resistance and achieves a higher on-to-off current ratio. Transmission electron microscopy and electrical measurements that separately evaluate the end and middle silicon nanowire segments indicate that a pure axial doping profile is achieved for the n+-p--n+ silicon nanowires without deleterious shell doping, which also indicates that the transistor switching of the axially-doped silicon nanowire is due to electron inversion of the p--body as opposed to the accumulation of p-type carriers. The top-gate and wrap-around-gate n+-p--n+ field effect transistors have significantly higher on-state current and on-to-off state current ratio than the uniformly-doped nanowire field effect devices. The effective electron mobility of the devices was estimated using a four-point top-gate structure that excludes source and drain contact resistance, and was found to follow the expected universal inversion layer mobility versus effective electric field trend. The field effect properties of wrap-around-gate devices are less sensitive to global-back-gate bias and thus provide better electrostatic control of the nanowire channel. Experiments on the synthesis of in situ axially-doped p+-n-p+ silicon nanowires were carried out using trimethylboron or diborane for the end-segment (source/drain) doping. Initial electrical measurement data suggest that diborane may cause simultaneous thin film deposition over the middle segment during the growth of top segment, while an axial doping profile with minimal radial coating is possible using silicon nanowires doped with trimethylboron due to its higher thermal stability compared to diborane. Because of the higher resistivity of the p+ silicon nanowires compared to the n+ nanowires, the on-state current measured from top-gate p+-n-p+ devices fabricated using trimethylboron-doped source/drain segments is an order lower than that of n+-p--n+ devices. More studies should be conducted to improve in situ p-type doping during vapor-liquid-solid silicon nanowire synthesis to lower the resistivity of the p+ silicon nanowire source/drain segments. Post-metallization annealing on thermally-oxidized Al metal top-gate n+-p--n+ silicon nanowire field effect devices was studied to reduce interface state density and to improve the subthreshold slope of the devices. During the annealing process, the hydrogen that is released from the reduced hydroxyl group at the gate oxide and Al gate interface passivates the interface states. It is found that excessive annealing causes significant gate sweep hysteresis and that this is likely due to trapped charge in the oxidized Al film. By optimizing the annealing conditions, a nearly ideal subthreshold slope is achieved at room temperature, which is expected to improve the effective carrier mobility in the silicon nanowire field effect devices.