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1. Towards Minimizing the Adverse Effects of Temperature on High Performance Digital Systems

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2. Design and Analysis of Heterogeneous Networks for Chip-Multiprocessors

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3. A GPU based implementation of Center Surround Distribution Distance Algorithm for Feature Recognition

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4. Exploring Power Reliability Tradeoffs in On-Chip Networks

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6. Redundancy and Parallelism Tradeoffs for Reliable, High-Performance Architectures

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7. Implications of Future Technologies on the Design of FPGAs

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8. RELIABILITY ANALYSIS AND OPTIMIZATION FOR NANOSCALE SYSTEM-ON-CHIP DESIGN

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9. Issues in low-power and reliable wireless commuication system design

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10. Network-on-Chip Architectures: A Holistic Design Exploration

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11. SOFT ERROR RATE SIMULATION AND INITIAL DESIGN CONSIDERATIONS OF NEUTRON INTERCEPTING SILICON CHIP (NISC)

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12. FAULT TOLERANT SIGNAL PROCESSING FOR VLSI CIRCUITS

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13. Clock Network and Phase-Locked Loop Power Estimation and Experimentation

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15. Design of High-Performance, Energy-Efficient, and Reliable Network-on-Chip (NoC) Architectures

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16. Sensor Network Interoperability and Reconfiguration through Mobile Agents

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17. DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS

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20. EXPLORING THE MEMORY HIERARCHY DESIGN WITH EMERGING MEMORY TECHNOLOGIES

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21. Energy-aware hardware and software optimizations for embedded systems

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22. System Level Power and Reliability Modeling

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23. HIGH-PERFORMANCE SIGNAL PROCESSING ON RECONFIGURABLE PLATFORMS

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24. ANALYSIS OF TWO-DIMENSIONAL MEDIAN FILTER HARDWARE IMPLEMENTATIONS FOR REAL-TIME VIDEO DENOISING

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25. A Comprehensive Approach to Design Network-on-Chip Architectures for SoC/Multicore Systems

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26. A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications

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27. ORCHESTRATING THE COMPILER AND MICROARCHITECTURE FOR REDUCING CACHE ENERGY

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30. A Configurable Platform for Sensor and Image Processing

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31. Quality of Service Provisioning in Clusters

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32. DESIGNING ENERGY-EFFICIENT AND RELIABLE CACHES AND INTERCONNECTS

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33. Secure Communications in Sensor Networks

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34. DEVELOPMENT OF AN ION TIME-OF-FLIGHT SPECTROMETER FOR NEUTRON DEPTH PROFILING

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35. CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS

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36. Addressing Reliability Issues in Performance-Critical Processor Structures

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37. Accessing Spatial Information in Resource-constrained and Resource-rich Environments

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38. A Reliable Design Flow for Platform FPGAs.

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39. Application-Aware On-Chip Networks

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40. Analysis of Failures in Nanoscale Devices

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42. SOFT ERRORS IN LOGIC CIRCUITS: ANALYSIS AND MODELING

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43. Influence of Emerging Technologies on Interconnect Architectures

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47. Power Management of Enterprise Storage Systems

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48. CLOSING THE GAP BETWEEN FPGAs AND ASICs: THE APPLICATIONS OF CLOCK SKEW SCHEDULING ON FPGAs

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50. EMBEDDED HARDWARE FACE DETECTION FOR DIGITAL SURVEILLANCE SYSTEMS

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53. DEVICE AND ARCHITECTURE CO-DESIGN FOR ULTRA-LOW POWER LOGIC USING EMERGING TUNNELING-BASED DEVICES

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55. ARCHITECTURAL LEVEL POWER ESTIMATION AND EXPERIMENTATION

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57. Design Exploration for Three-dimensional Integrated Circuits (3DICs)

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58. Modeling and Leveraging Emerging Non-Volatile Memories for Future Computer Designs

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59. VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS

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60. Mobile Agent-Based Energy-Efficient and Secure Global Information Systems

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62. Domain-specific Accelerators on Reconfigurable Platforms

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63. Architecting On-Chip Interconnection Network for Future Many-Core Chip-Multiprocessors

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64. Design Fabrication and Characterization of Antimonide MOS Transistors

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65. Accelerating Cortical Processing for Real Time Neuromorphic Vision Systems

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66. A Game Theoretic Approach to Multi-agent Systems in Highly Dynamic, Information-sparse, Role Assignment Scenarios

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67. Accelerating Design and Implementation of Embedded Vision Systems

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68. Tracing footprints of Environmental events in tree ring chemistry using Neutron Activation Analysis

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69. Arsendie-Antmonide Tunnel Transistors for Low Power Logic Applications

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70. Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity

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71. Modeling and Architecting Emerging Non-volatile Resistive Random Access Memory for Future Computer System

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72. system-on-chip integration of heterogeneous accelerators for perceptual computing

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74. Classical And Coulomb Blockade Iii-v Multi-gate Quantum Well Field Effect Transistors For Ultra Low Power Logic Applications

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75. Utilizing Graphics Processing Units for Rapid Facial Recognition using Video Input

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76. A Study of DRAM Optimization to Break the Memory Wall

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77. Rethinking the memory hierarchy design with nonvolatile memory technologies

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78. Configurable Accelerators for Visual and Text Analytics

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79. using attention to enhance efficiency in video-based computer systems

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80. An examination of Post-CMOS computing techniques using steep-slope device-based architectures

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81. Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory

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83. Device Circuit Interactions for Steep Switching Slope Devices

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84. design methodologies of three-dimensional integrated circuits (3D ICs)

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86. Enabling Intelligent Vision Systems in a Configurable Multi-algorithm Pipeline

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88. Real Time Object Tracking On Active Pan Tilt Zoom Camera Using Cmt

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89. A High-efficiency Switched-capacitance Htfet Charge Pump For Low-input-voltage Applications

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90. Optimization and Hardware Acceleration of Consensus-based Matching and Tracking

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91. Architecting Byte-addressable Non-volatile Memories for Main Memory

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92. Three Dimensional Integrated Circuit Design and Test

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93. Variation Study on Advanced Cmos Systems for Low Voltage Applications

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96. Large-Scale Object Recognition for Embedded Wearable Platforms

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97. COMPLIMENTARY III-V HETERO-JUNCTION TUNNEL TRANSISTORS FOR ENERGY EFFICIENT NANOELECTRONICS

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98. EXPLOITING AND ACCOMMODATING ASYMMETRIES IN MEMORY TO ENABLE EFFICIENT MULTI-CORE SYSTEMS

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99. DIGITAL/MIXED-SIGNAL CIRCUIT DESIGNS WITH STEEP SLOPE III-V TUNNEL TRANSISTORS

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100. PREDICTION AND ASSESSMENT OF AMBIENT ENERGY SIGNALS FOR ENERGY HARVESTING SYSTEMS

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